公开(公告)号：US10052705B2

公开(公告)日：2018-08-21

申请号：US14413121

申请日：2013-08-29

申请人： UNIVERSAL INSTRUMENTS CORPORATION

发明人： Koenraad Alexander Gieskes

IPC分类号： B23K1/00 ,  B23K3/08 ,  H01L23/00 ,  H01L25/00 ,  B23K3/04 ,  H01L25/065

CPC分类号： B23K3/087 ,  B23K1/0008 ,  B23K1/0016 ,  B23K3/04 ,  B23K2035/008 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/75272 ,  H01L2224/7555 ,  H01L2224/7565 ,  H01L2224/75745 ,  H01L2224/81005 ,  H01L2224/81011 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/81

摘要： Disclosed herein is a method that includes picking up a plate with a nozzle, the plate including at least one opening to allow air to flow therethrough. The method includes picking up a die with the nozzle such that the plate is located between the nozzle and the die. The method includes placing the die and the plate onto a device, substrate or another die such that the plate is located on top of the die. The method includes heating the device, substrate or another die and the die in a heat chamber while the plate remains on top of the die to permanently attach the die to the device, substrate or another die. Further disclosed herein is an assembly system configured to perform a method that utilizes the plate and die combination for attaching the die to a device, substrate or another die by heating.

公开(公告)号：US20180158797A1

公开(公告)日：2018-06-07

申请号：US15869673

申请日：2018-01-12

申请人： International Business Machines Corporation

发明人： Charles L. Arvin ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/00 ,  H01L21/52 ,  H01L21/56 ,  H01L21/48

CPC分类号： H01L24/81 ,  B23K35/025 ,  B23K35/262 ,  B23K35/302 ,  B23K35/3033 ,  H01L21/4853 ,  H01L21/52 ,  H01L21/563 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13211 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13447 ,  H01L2224/13455 ,  H01L2224/13541 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/17505 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/8112 ,  H01L2224/81193 ,  H01L2224/81211 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/81911 ,  H01L2924/0132 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/00012

摘要： A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

公开(公告)号：US09911683B2

公开(公告)日：2018-03-06

申请号：US13642325

申请日：2011-04-18

申请人： Naohide Takamoto ,  Goji Shiga

发明人： Naohide Takamoto ,  Goji Shiga

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/683 ,  H01L21/50 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544

CPC分类号： H01L23/48 ,  H01L21/50 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2223/54486 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/83862 ,  H01L2224/92125 ,  H01L2924/01019 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/3512

摘要： The film for back surface of flip-chip semiconductor according to the present invention is a film for back surface of flip-chip semiconductor to be formed on a back surface of a semiconductor element having been flip-chip connected onto an adherend, wherein a tensile storage elastic modulus at 23° C. after thermal curing is 10 GPa or more and not more than 50 GPa. According to the film for back surface of flip-chip semiconductor of the present invention, since it is formed on the back surface of a semiconductor element having been flip-chip connected onto an adherend, it fulfills a function to protect the semiconductor element. In addition, since the film for back surface of flip-chip semiconductor according to the present invention has a tensile storage elastic modulus at 23° C. after thermal curing of 10 GPa or more, a warp of the semiconductor element generated at the time of flip-chip connection of a semiconductor element onto an adherend can be effectively suppressed or prevented.

公开(公告)号：US09786622B2

公开(公告)日：2017-10-10

申请号：US13277575

申请日：2011-10-20

申请人： Ming-Da Cheng ,  Chih-Wei Lin ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Chun-Cheng Lin ,  Chung-Shi Liu

发明人： Ming-Da Cheng ,  Chih-Wei Lin ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Chun-Cheng Lin ,  Chung-Shi Liu

IPC分类号： H01L23/488 ,  H01L23/00

CPC分类号： H01L24/16 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05572 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/1601 ,  H01L2224/16104 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/206 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The distance between the conductive pillar and the conductive trace is less than or equal to about 16 μm.

公开(公告)号：US20170179071A1

公开(公告)日：2017-06-22

申请号：US15244069

申请日：2016-08-23

申请人： International Business Machines Corporation

发明人： Charles L. Arvin ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/00 ,  H01L21/52 ,  H01L21/56 ,  H01L21/48

CPC分类号： H01L24/81 ,  B23K35/025 ,  B23K35/262 ,  B23K35/302 ,  B23K35/3033 ,  H01L21/4853 ,  H01L21/52 ,  H01L21/563 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13211 ,  H01L2224/13347 ,  H01L2224/13355 ,  H01L2224/13447 ,  H01L2224/13455 ,  H01L2224/13541 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/17505 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/8112 ,  H01L2224/81193 ,  H01L2224/81211 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/81911 ,  H01L2924/0132 ,  H01L2924/01074 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/00012

摘要： A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder bump including a nickel copper colloid surrounded by a nickel or copper shell and suspended in a tin-based solder; aligning the chip with the laminate; performing a first reflow process to join the chip to the laminate; depositing an underfill material around the first solder bump and the second solder bump; and performing a second reflow process at a temperature that is lower than the first reflow process to convert the first solder bump and the second solder bump to an all intermetallic interconnect; wherein depositing the underfill material is performed before or after performing the second reflow process.

公开(公告)号：US20170141060A1

公开(公告)日：2017-05-18

申请号：US15419924

申请日：2017-01-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Wei Chen ,  Yi-Wen Wu

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L21/02

CPC分类号： H01L24/11 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/768 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/564 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with an opening to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is then removed to expose a portion of the PPI structure. A solder bump is then formed over and electrically connected to the first portion of the PPI structure.

公开(公告)号：US09159589B2

公开(公告)日：2015-10-13

申请号：US14210817

申请日：2014-03-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Jing-Cheng Lin ,  Cheng-Lin Huang

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L24/16 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/81911 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014

摘要： A method of forming a chip package includes providing a chip with a plurality of first copper post bumps having a first height of copper post. The method also includes providing a substrate with a plurality of second copper post bumps having a second height of copper post. The method further includes bonding the plurality of first copper post bumps to the plurality of second copper post bumps by reflowing solder layers on the plurality of first copper post bumps and the plurality of second copper post bumps together to form a first copper post bump structure of the chip package. The first copper post bump structure has a standoff, wherein a ratio of a sum of the first height of copper post and the second height of copper post to the standoff is equal to or greater than about 0.6 and less than 1.

摘要翻译： 形成芯片封装的方法包括向芯片提供具有铜柱第一高度的多个第一铜柱凸起。 该方法还包括向基板提供具有铜柱第二高度的多个第二铜柱凸起。 该方法还包括通过将多个第一铜柱凸点上的焊料层和多个第二铜柱凸点一起回流焊接而将多个第一铜柱凸点接合到多个第二铜柱凸起，以形成第一铜柱凸起结构 芯片封装。 第一铜柱凸起结构具有间隔，其中铜柱的第一高度和铜柱的第二高度之和与间隙的比等于或大于约0.6且小于1。

公开(公告)号：US20150158103A1

公开(公告)日：2015-06-11

申请号：US14612310

申请日：2015-02-03

申请人： SAN-EI KAGAKU CO., LTD.

发明人： Kazunori KITAMURA ,  Yasuhiro TAKASE ,  Kazuki HANADA

IPC分类号： B23K1/20 ,  H05K13/04 ,  B23K1/00

CPC分类号： H05K3/305 ,  B23K1/0016 ,  B23K1/20 ,  C08G59/42 ,  C08L63/00 ,  H01L21/563 ,  H01L23/3135 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81395 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83862 ,  H01L2224/92125 ,  H01L2924/01029 ,  H01L2924/13055 ,  H05K3/341 ,  H05K13/0465 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/014

摘要： A surface mounting method includes applying an active resin composition to at least part of a surface of a printed wiring substrate; mounting a surface mount device on the substrate; performing reflow soldering; applying an under-filling resin into a space of interest; before and/or after applying the under-filling resin, performing a vacuum treatment and/or heating at a temperature lower than the curing reaction-initiating temperature of any of the applied active resin composition and the under-filling resin; and subsequently, thermally curing the resin composition and the under-filling resin. The active resin composition contains an epoxy resin in an amount of 100 parts by weight, a blocked carboxylic acid compound in an amount of 1-50 parts by weight and/or a carboxylic acid compound in an amount of 1-10 parts by weight, and a curing agent which can initiate curing reaction at 150° C. or higher, in an amount of 1-30 parts by weight.

摘要翻译： 表面安装方法包括将活性树脂组合物施加到印刷布线基板的至少一部分表面上; 将表面安装装置安装在基板上; 进行回流焊接; 将未充满的树脂施加到感兴趣的空间中; 在施加未充填树脂之前和/或之后，在低于所施加的活性树脂组合物和未充填树脂的固化反应引发温度的温度下进行真空处理和/或加热; 然后将树脂组合物和未填充树脂热固化。 活性树脂组合物含有100重量份的环氧树脂，1-50重量份的封端羧酸化合物和/或1-10重量份的羧酸化合物， 和可以在150℃以上引发固化反应的固化剂，其量为1-30重量份。

公开(公告)号：US08987899B2

公开(公告)日：2015-03-24

申请号：US13357046

申请日：2012-01-24

申请人： Hiroshi Asami

发明人： Hiroshi Asami

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H05K1/11 ,  H05K3/34 ,  H05K3/28 ,  H01L23/00

CPC分类号： H01L23/49816 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/00013 ,  H01L2924/12042 ,  H05K1/111 ,  H05K3/28 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/099 ,  H05K2203/0315 ,  H05K2203/043 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2224/11 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00

摘要： A circuit board includes: an electrode portion which has a copper layer, a copper oxide layer formed thereon, and a removal portion formed by partially removing the copper oxide layer so as to partially expose the copper layer from the copper oxide layer; and a solder bump for flip chip mounting formed on the copper layer exposed by the removal portion.

摘要翻译： 电路板包括：具有铜层，形成在其上的氧化铜层的电极部分和通过部分去除氧化铜层而形成的去除部分，以从铜氧化物层部分地露出铜层; 以及在由去除部分露出的铜层上形成的用于倒装芯片安装的焊料凸块。

公开(公告)号：US08986486B2

公开(公告)日：2015-03-24

申请号：US13170581

申请日：2011-06-28

申请人： Naohide Takamoto ,  Goji Shiga ,  Fumiteru Asai

发明人： Naohide Takamoto ,  Goji Shiga ,  Fumiteru Asai

IPC分类号： B32B38/04 ,  C09J7/02 ,  H01L21/56 ,  H01L21/683 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L23/544

CPC分类号： H01L21/6836 ,  B32B37/1284 ,  B32B38/0004 ,  B32B38/10 ,  B32B2405/00 ,  B32B2457/14 ,  C09J7/20 ,  C09J165/00 ,  C09J2201/606 ,  C09J2203/326 ,  C09J2461/00 ,  C09J2463/00 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3164 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68336 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/5448 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/27003 ,  H01L2224/27436 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29386 ,  H01L2224/73204 ,  H01L2224/81095 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/15787 ,  H01L2924/15788 ,  Y10T156/1052 ,  Y10T156/1064 ,  Y10T156/1075 ,  Y10T156/1077 ,  Y10T156/1082 ,  Y10T156/1093 ,  Y10T428/1471 ,  Y10T428/1476 ,  Y10T428/1495 ,  Y10T428/15 ,  Y10T428/21 ,  H01L21/78 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2224/13099

摘要： The present invention relates to a film for semiconductor device production, which includes: a separator; and a plurality of adhesive layer-attached dicing tapes each including a dicing tape and an adhesive layer laminated on the dicing tape, which are laminated on the separator at a predetermined interval in such a manner that the adhesive layer attaches to the separator, in which the separator has a cut formed along the outer periphery of the dicing tape, and the depth of the cut is at most ⅔ of the thickness of the separator.

摘要翻译： 本发明涉及一种用于半导体器件生产的膜，其包括：隔板; 以及多个粘附层附着的切割带，每个粘合剂层附着的切割带包括层合在切割带上的切割带和粘合剂层，它们以预定的间隔层压在隔板上，使得粘合剂层附着到隔板上，其中 分离器具有沿着切割带的外周形成的切口，并且切割深度为隔板的厚度的至多。。