公开(公告)号：US20240332272A1

公开(公告)日：2024-10-03

申请号：US18190885

申请日：2023-03-27

Applicant: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.

Inventor： Sang Yun MA ,  Dong Hee KANG

IPC: H01L25/16 ,  H01L23/13 ,  H01L23/367 ,  H01L23/552

CPC classification number: H01L25/165 ,  H01L23/13 ,  H01L23/3675 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/0132 ,  H01L2924/0665 ,  H01L2924/069 ,  H01L2924/0695 ,  H01L2924/07025 ,  H01L2924/0715

Abstract: In one example, an electronic device includes a substrate with a substrate first side; a substrate second side opposite to the substrate first side, a substrate lateral side connecting the substrate first side to the substrate second side, a dielectric structure, and a conductive structure. A substrate dock includes a substrate dock base at the substrate first side and a first substrate dock sidewall extending upward from the substrate dock base. The substrate dock base and the first substrate dock sidewall define a substrate dock cavity. A cover structure includes a cover sidewall with a cover sidewall lower side. An interface material couples the cover sidewall to the substrate dock. An electronic component is coupled to the conductive structure. Other examples and related methods are also disclosed herein.

公开(公告)号：US12107035B2

公开(公告)日：2024-10-01

申请号：US17897556

申请日：2022-08-29

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Jae Yun Kim ,  Gi Tae Lim ,  Woon Kab Jung ,  Ju Hoon Yoon ,  Dong Joo Park ,  Byong Woo Cho ,  Gyu Wan Han ,  Ji Young Chung ,  Jin Seong Kim ,  Do Hyun Na

IPC: H01L23/498 ,  H01L21/50 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/50 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/92 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8321 ,  H01L2224/92225 ,  H01L2224/92242 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/8321 ,  H01L2924/00014 ,  H01L2224/83203 ,  H01L2924/00014 ,  H01L2224/2929 ,  H01L2924/0665 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2224/293 ,  H01L2924/00014 ,  H01L2224/92242 ,  H01L2224/81 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/1329 ,  H01L2924/00014 ,  H01L2224/133 ,  H01L2924/00014

Abstract: A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.

公开(公告)号：US12080660B2

公开(公告)日：2024-09-03

申请号：US17228978

申请日：2021-04-13

Applicant: CREE, INC.

Inventor： Xikun Zhang ,  Dejiang Chang ,  Bill Agar ,  Michael Lefevre ,  Alexander Komposch

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H01L25/00 ,  H01L25/07 ,  H01L29/16

CPC classification number: H01L23/66 ,  H01L23/49503 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  H01L24/95 ,  H01L25/072 ,  H01L25/50 ,  H01L29/16 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49582 ,  H01L23/49586 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L2223/6644 ,  H01L2223/6672 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83121 ,  H01L2224/83136 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/83855 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2224/29101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/29144 ,  H01L2924/0105 ,  H01L2224/29139 ,  H01L2924/0105 ,  H01L2224/29147 ,  H01L2924/0105 ,  H01L2224/83855 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2224/92247 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00012

Abstract: A multi-die package includes a thermally conductive flange, a first semiconductor die made of a first semiconductor material attached to the thermally conductive flange via a first die attach material, a second semiconductor die attached to the same thermally conductive flange as the first semiconductor die via a second die attach material, and leads attached to the thermally conductive flange or to an insulating member secured to the flange. The leads are configured to provide external electrical access to the first and second semiconductor dies. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. Additional multi-die package embodiments are described.

公开(公告)号：US12080637B2

公开(公告)日：2024-09-03

申请号：US17725627

申请日：2022-04-21

Applicant: Dai Nippon Printing Co., Ltd.

Inventor： Satoru Kuramochi ,  Sumio Koiwa ,  Hidenori Yoshioka

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L25/18 ,  H05K1/11 ,  H05K3/28 ,  H05K3/44 ,  H01L23/00 ,  H01L23/13 ,  H01L23/15

CPC classification number: H01L23/49827 ,  H01L23/481 ,  H01L23/49894 ,  H01L25/065 ,  H01L25/18 ,  H05K1/115 ,  H05K3/28 ,  H05K3/445 ,  H01L23/13 ,  H01L23/15 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/81805 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/381 ,  H05K2201/09154 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/0959 ,  H05K2201/09854 ,  H05K2203/0594 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/15787 ,  H01L2924/05432 ,  H01L2924/1579 ,  H01L2924/00014 ,  H01L2224/13109 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/81805 ,  H01L2924/00014 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2224/2919 ,  H01L2924/0665 ,  H01L2224/2919 ,  H01L2924/07025

Abstract: A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

公开(公告)号：US12057377B2

公开(公告)日：2024-08-06

申请号：US17838949

申请日：2022-06-13

Applicant: Magnachip Semiconductor, Ltd.

Inventor： Hyun Dong Kim

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49537 ,  H01L21/56 ,  H01L21/565 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/29 ,  H01L24/45 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45616 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48175 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83851 ,  H01L2224/92247 ,  H01L2924/00011 ,  H01L2924/0665 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45565 ,  H01L2224/45147 ,  H01L2224/45616 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/01005

Abstract: A multichip package and a method for manufacturing the same are provided. A multichip package includes: a plurality of semiconductor chips each mounted on corresponding lead frame pads; lead frames connected to the semiconductor chips by a bonding wire; and fixed frames integrally formed with at least one of the lead frame pads and configured to support the lead frame pads on a package-forming substrate.

公开(公告)号：US12051639B2

公开(公告)日：2024-07-30

申请号：US17684416

申请日：2022-03-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chiang Tsao ,  Chao-Wei Chiu ,  Jen-Jui Yu ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L23/367 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/4867 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13655 ,  H01L2224/13686 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/1058 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0665

Abstract: A package structure includes a first package, a second package, a conductive spacer, and a flux portion. The first package includes a semiconductor die. The second package is stacked to the first package. The conductive spacer is disposed between and electrically couples the first package and the second package. The flux portion is disposed between and electrically couples the first package and the conductive spacer, where the flux portion includes a first portion and a second portion separating from the first portion by a gap, and the first portion and the second portion are symmetric about an extending direction of the gap. The gap is overlapped with the conductive spacer.

公开(公告)号：US20240243114A1

公开(公告)日：2024-07-18

申请号：US18414485

申请日：2024-01-17

Applicant: Acer Incorporated

Inventor： Yu-Ming Lin ,  Mao-Neng Liao ,  Cheng-Wen Hsieh ,  Kuang-Hua Lin ,  Wei-Chin Chen ,  Kuan-Lin Chen ,  Chun-Chieh Wang

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/24 ,  H05K7/20

CPC classification number: H01L25/165 ,  H01L23/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H05K7/20445 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33183 ,  H01L2924/0665 ,  H01L2924/1432

Abstract: An electronic package structure includes first and second package modules combined with each other. The first package module includes a substrate and a first electronic component disposed thereon, at least one second electronic component, and an insulation film. The first electronic component and the second electronic component are adjacent to each other. The insulation film includes a base material and a foam glue body, and the foam glue body is viscous and compressible. The second package module includes a heat dissipation plate and a liquid metal and an insulation protrusion portion disposed thereon. The liquid metal is pressed by the heat dissipation plate and the first electronic component. The insulation protrusion portion covers and abuts against the insulation film to press the foam glue body through the base material so as to deform the foam glue body and enable the foam glue body to cover the second electronic component.

公开(公告)号：US20240227089A9

公开(公告)日：2024-07-11

申请号：US18271531

申请日：2022-01-20

Applicant: SEKISUI CHEMICAL CO., LTD.

Inventor： Hidefumi YASUI ,  Kiyoto MATSUSHITA

IPC: B23K35/36 ,  B23K35/02 ,  C08G59/24 ,  C08G59/42 ,  C08G59/68 ,  H01L23/00 ,  H05K3/34 ,  H05K3/36

CPC classification number: B23K35/3613 ,  B23K35/025 ,  C08G59/245 ,  C08G59/4238 ,  C08G59/688 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H05K3/3436 ,  H05K3/3489 ,  H05K3/368 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/0568 ,  H01L2224/05684 ,  H01L2224/1369 ,  H01L2224/27422 ,  H01L2224/29078 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/81815 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2924/0665 ,  H05K2203/0485

Abstract: Provided is a non-electroconductive flux capable of enhancing productivity and impact resistance of a connected structure to be obtained and suppressing occurrence of solder flash. The non-electroconductive flux according to the present invention contains an epoxy compound, an acid anhydride curing agent, and an organophosphorus compound.

公开(公告)号：US20240213112A1

公开(公告)日：2024-06-27

申请号：US18169212

申请日：2023-02-15

Applicant: GLOBAL UNICHIP CORPORATION ,  TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sheng-Fan YANG ,  Yen-Chao LIN ,  Chi-Ming YANG

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/3675 ,  H01L23/3185 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L24/29 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32257 ,  H01L2224/32258 ,  H01L2224/33181 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2924/0665 ,  H01L2924/1616 ,  H01L2924/16235 ,  H01L2924/18161

Abstract: A semiconductor packaging device includes a packaging module, a heat dissipation cover and a thermal interface material layer. The package module includes a substrate, and a working chip mounted on the substrate. The heat dissipation cover includes a metal cover fixed on the substrate and covering the working chip, an accommodating recess located on the metal cover to accommodate the working chip, and a plurality of protrusive columns respectively formed on the metal cover and distributed within the accommodating recess at intervals. The depth of the accommodating recess is greater than the height of each protrusive column, and the accommodating recess is greater than the working chip. The thermal interface material layer is non-solid, and located within the accommodating recess between the protrusive columns to wrap the protrusive columns and contact with the working chip, the metal cover and the protrusive columns.

公开(公告)号：US20240170473A1

公开(公告)日：2024-05-23

申请号：US18347594

申请日：2023-07-06

Applicant: Industrial Technology Research Institute

Inventor： Hao-Che Kao ,  Wen-Hung Liu ,  Yu-Min Lin ,  Ching-Kuan Lee

IPC: H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/49822 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/95 ,  H01L25/0655 ,  H01L21/4853 ,  H01L24/16 ,  H01L24/73 ,  H01L2221/68381 ,  H01L2224/16227 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/0665

Abstract: A chip package structure including a heat dissipation base, a first redistribution layer, a second redistribution layer, at least one chip, at least one metal stack, a plurality of conductive structures, and an encapsulant is provided. The second redistribution layer is disposed on the heat dissipation base and thermally coupled to the heat dissipation base. The chip, the metal stack, and the conductive structures are disposed between the second redistribution layer and the first redistribution layer. An active surface of the chip is electrically connected to the first redistribution layer and an inactive surface of the chip is thermally coupled to the second redistribution layer via the metal stack. The first redistribution layer is electrically connected to the second redistribution layer via the conductive structures. The encapsulant is filled between the second redistribution layer and the first redistribution layer. A manufacturing method of a chip package structure is also provided.