公开(公告)号：US20250072129A1

公开(公告)日：2025-02-27

申请号：US18480750

申请日：2023-10-04

Applicant: Taiwan-Asia Semiconductor Corporation

Inventor： Di-Bao WANG

IPC: H01L31/112 ,  H01L29/16 ,  H01L29/51 ,  H01L29/66 ,  H01L31/101

Abstract: A monolithic Opto-MOSFET relay and manufacturing method thereof are provided. The manufacturing method of the monolithic Opto-MOSFET relay involves using a low ion doping concentration substrate. In this method, a first P-N junction structure, a second P-N junction structure, and an N-P-N junction structure are formed within an epitaxial layer. Dry etching is employed to divide the epitaxial layer into a high-voltage region and a low-voltage region, which are electrically isolated from the each other. Subsequently, an isolation layer is deposited on the epitaxial layer, and photomask etching is performed to generate multiple patterns. A metal layer is then deposited to form a light emitting diode (LED) based on the pattern within the first P-N junction structure, a photodiode within the second P-N junction structure, and at least one MOSFET within the N-P-N junction structure.

公开(公告)号：US20250072021A1

公开(公告)日：2025-02-27

申请号：US18237034

申请日：2023-08-23

Applicant: Unity Power Technology Limited

Inventor： Wai Tien CHAN

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78

Abstract: A silicon carbide MOSFET device which contains a N-Channel MOSFET, and a JFET connected to the N-Channel MOSFET such that their drain-source current paths are connected in series. A gate of the JFET is connected to a gate of the N-Channel MOSFET device via a voltage divider, which is formed monolithically with the silicon carbide substrate and the first to fourth silicon carbide layers. The protection gate structure can shield the trench oxide from high drain voltage during off-state. The voltage divider is configured to restrict a gate voltage of the JFET such that a SiC PN diode formed within the silicon carbide MOSFET device is turned off when the N-Channel MOSFET is on or off.

公开(公告)号：US12237410B1

公开(公告)日：2025-02-25

申请号：US18937369

申请日：2024-11-05

Applicant: JSAB TECHNOLOGIES (SHENZHEN) LTD.

Inventor： Yong Liu ,  Hao Feng ,  Xin Peng ,  Johnny Kin On Sin

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66

Abstract: A trench gate silicon carbide metal oxide semiconductor field effect transistor (MOSFET) device and a fabrication method thereof. A second conductive heavily doped layer at the bottom corner of a trench gate is electrically connected to a second conductive heavily doped layer on another side edge of the trench gate through a layout design, which ensures a ground potential during voltage blocking state. This design protects the insulating layer in the trench gate and the Schottky contact in a junction barrier Schottky (JBS) diode, thereby enhancing device reliability. Moreover, in a diode operating mode, P+ on the left and right sides of the trench gate are connected to a positive potential. When the P+/N− junction is activated, the conductivity modulation can be implemented through hole injection, thereby improving the device's ability to withstand surge current impacts.

公开(公告)号：US20250063800A1

公开(公告)日：2025-02-20

申请号：US18449458

申请日：2023-08-14

Applicant: Wolfspeed, Inc.

Inventor： Thomas Edgar Harrington, III

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/16 ,  H01L29/49 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

Abstract: Wide bandgap trench gate semiconductor devices are provided. In one example, a semiconductor device includes a wide bandgap semiconductor structure. The wide bandgap semiconductor structure includes a drift region of a first conductivity type and a well region of a second conductivity type. The semiconductor device includes a gate trench in the wide bandgap semiconductor structure. The gate trench extends through the well region into the drift region. The semiconductor device includes a buried gate structure in the gate trench. The buried gate structure includes a gate polysilicon layer and a gate silicide layer.

公开(公告)号：US20250063774A1

公开(公告)日：2025-02-20

申请号：US18234083

申请日：2023-08-15

Applicant: Nami MOS CO., LTD.

Inventor： FU-YUAN HSIEH ,  LIN XU

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/40 ,  H01L29/78

Abstract: An improved SiC trench MOSFET having N-type and P-type shield zones for gate oxide electric-field reduction is disclosed. The N-type shield zones are formed below a gate electrode and the P-type shield zones adjoin lower surfaces of the body regions. The device further comprises a current spreading region surrounding at least sidewalls of the gate trenches for on-resistance reduction.

公开(公告)号：US20250063760A1

公开(公告)日：2025-02-20

申请号：US18769255

申请日：2024-07-10

Applicant: SUZHOU WATECH ELECTRONICS CO., LTD.

Inventor： Changchang WANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/16 ,  H01L29/417 ,  H01L29/66

Abstract: Disclosed are a lateral silicon carbide junction gate field effect transistor (SiC-JFET) device and a manufacturing method thereof. The lateral SiC-JFET device includes a base; a source and a drift region formed on the base in sequence; a first source contact region, a second source contact region, and a channel region formed on the source in sequence; and a gate formed on the channel region; where the channel region and the drift region are independent structures respectively. The embodiments of the present disclosure solved the technical problem that the adjustment of the breakdown voltage of the conventional lateral SiC-JFET device is limited by the size of the channel region.

公开(公告)号：US20250063748A1

公开(公告)日：2025-02-20

申请号：US18235161

申请日：2023-08-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Francois Hebert ,  James A. Cooper

IPC: H01L29/739 ,  H01L29/16 ,  H01L29/66 ,  H01L29/861

Abstract: Structures for an insulated-gate bipolar transistor and methods of forming a structure for an insulated-gate bipolar transistor. The structure comprises a semiconductor substrate having a front surface and a back surface opposite from the front surface. The semiconductor substrate comprises a wide bandgap semiconductor material. The structure further comprises a gate electrode at the front surface of the semiconductor substrate, and a diode at the back surface of the semiconductor substrate.

公开(公告)号：US12230699B2

公开(公告)日：2025-02-18

申请号：US17067988

申请日：2020-10-12

Applicant: Analog Devices, Inc.

Inventor： Daniel Piedra ,  James G. Fiorenza ,  Puneet Srivastava

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

Abstract: Integrated circuits can include semiconductor devices with back-side field plates. The semiconductor devices can be formed on substrates that have conductive layers located within the substrates. The conductive layers can include at least one of a conducting material or a semi-conducting material that modifies an electric field produced by the semiconductor devices. The semiconductor devices can include one or more semiconductor layers that include one or more materials having a compound material that includes at least one Group 13 element and at least one Group 15 element.

公开(公告)号：US20250056830A1

公开(公告)日：2025-02-13

申请号：US18716653

申请日：2022-12-14

Applicant: Robert Bosch GmbH

Inventor： Daniel Krebs ,  Alberto Martinez-Limia ,  Jens Baringhaus

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

Abstract: A method for producing a power FinFET with two-part control electrodes. The method includes: creating a first structured mask including oxide regions and first and second open regions on the front side of a semiconductor body via lithography; creating first and second trenches below the first and second open regions, respectively, by a first etching process starting from the front side of the semiconductor body into the drift layer, the first and second trenches being arranged substantially parallel to one another and alternate, the second trenches have a smaller width than the first trenches; applying a polysilicon layer onto the front side so that the first and second trenches are filled; applying an isotropic oxide layer onto the front side of the semiconductor body; creating a second structured mask on the isotropic oxide layer via lithography, wherein the second structured mask is open above the first trenches.

公开(公告)号：US12224358B2

公开(公告)日：2025-02-11

申请号：US17584185

申请日：2022-01-25

Applicant: STMicroelectronics S.r.l.

Inventor： Simone Rascuna′ ,  Gabriele Bellocchi ,  Marco Santoro

IPC: H01L29/872 ,  H01L21/04 ,  H01L29/16 ,  H01L29/66

Abstract: A Junction Barrier Schottky device includes a semiconductor body of SiC having a first conductivity. An implanted region having a second conductivity, extends into the semiconductor body from a top surface of the semiconductor body to form a junction barrier diode with the semiconductor body. An electrical terminal is in ohmic contact with the implanted region and in direct electrical contact with the top surface, laterally to the implanted region, to form a Schottky diode with the semiconductor body. The implanted region is formed by a first and a second portion electrically connected directly to each other and aligned along an alignment axis transverse to the top surface. Orthogonally to the alignment axis, the first portion has a first maximum width and the second portion has a second maximum width greater than the first maximum width.