公开(公告)号：US12114424B2

公开(公告)日：2024-10-08

申请号：US17639323

申请日：2020-04-24

Applicant: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd. ,  Avary Holding (Shenzhen) Co., Limited.

Inventor： Mei Yang ,  Gang Yuan

IPC: H05K1/11 ,  H03K3/42 ,  H05K3/06 ,  H05K3/42

CPC classification number: H05K1/115 ,  H05K3/067 ,  H05K3/423 ,  H05K2201/09227 ,  H05K2201/09563

Abstract: A circuit board and a manufacturing method therefor. The circuit board includes a substrate and a plurality of traces arranged at intervals on the substrate. Each trace includes a seed layer located on one surface of the substrate, a first copper layer located on the surface of the seed layer away from the substrate, and a second copper layer plated on one surface of the substrate. The second copper layer covers the seed layer and the first copper layer. The ratio of the thickness of each trace to the space between any two adjacent traces is greater than 1. The thickness of the second copper layer in the thickness direction of the substrate is greater than the thickness of the second copper layer in a direction perpendicular to the thickness direction of the substrate.

公开(公告)号：US20240284608A1

公开(公告)日：2024-08-22

申请号：US18611934

申请日：2024-03-21

Applicant: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd. ,  Avary Holding (Shenzhen) Co., Limited. ,  Garuda Technology Co., Ltd.

Inventor： Gang Yuan ,  Xiao-Juan Zhang

IPC: H05K5/00 ,  H05K1/05 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40

CPC classification number: H05K5/0069 ,  H05K1/056 ,  H05K1/112 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/4038 ,  H05K2201/09563 ,  H05K2201/10128 ,  H05K2203/0323

Abstract: A circuit board includes an inner wiring substrate and a first side plate. The inner wiring substrate includes a plurality of first connection pads at a side. The first side plate is disposed on the inner wiring substrate and defines a plurality of first holes exposing the first connection pads. Each first hole includes a first end facing the first connection pad and a second end facing away from the first connection pad. A central distance between two adjacent first connection pads is greater than a center distance between two second ends of two adjacent first holes. The first holes are filled with first conductive bodies, each first conductive body is electrically connected to the first connection pad and extends out of the first hole to form a connection portion. A method for manufacturing the circuit board and a display module are also disclosed.

公开(公告)号：US12035484B2

公开(公告)日：2024-07-09

申请号：US17610060

申请日：2020-03-31

Applicant: NITTO DENKO CORPORATION

Inventor： Kenya Takimoto ,  Naoki Shibata ,  Hayato Takakura

IPC: H05K3/44 ,  H05K1/11

CPC classification number: H05K3/445 ,  H05K1/115 ,  H05K2201/09563 ,  H05K2203/0323 ,  H05K2203/0723

Abstract: A wiring circuit board includes a metal support layer, a base insulating layer disposed on one side in a thickness direction of the metal support layer, and a conductive layer disposed on one side in the thickness direction of the base insulating layer, and including a first terminal and a ground lead residual portion electrically connected to the first terminal. The base insulating layer has a through hole penetrating in the thickness direction. The ground lead residual portion has an opening continuous so as to surround the through hole.

公开(公告)号：US20240096774A1

公开(公告)日：2024-03-21

申请号：US18262986

申请日：2021-11-11

Applicant: TOYOBO CO., LTD.

Inventor： Tetsuo OKUYAMA ,  Keisuke MATSUO

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/4644 ,  H05K2201/0154 ,  H05K2201/09563

Abstract: This method for producing a layered body includes: a step A for preparing a first layered body by layering a first resin film and a patterned metal layer; a step B for preparing a second resin film having indentations corresponding to the metal layer pattern; and a step C for mating the metal layer pattern and the indentations in the second resin film and bonding together the first layered body and second resin film.

公开(公告)号：US20240080994A1

公开(公告)日：2024-03-07

申请号：US18446544

申请日：2023-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gun Lee ,  Junwoo Myung ,  Yuseon Heo

IPC: H05K3/46 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K3/465 ,  H05K1/0296 ,  H05K1/0306 ,  H05K1/114 ,  H05K3/0023 ,  H05K3/4661 ,  H05K3/4679 ,  H05K2201/09563 ,  H05K2201/096

Abstract: In fabricating a wiring structure, a first wiring is formed on a substrate. First and second light sensitive insulation layers that are reactive to light of first and second wavelength ranges, respectively, are sequentially formed on the first wiring. First and second exposing processes are performed using the light of the first and second wavelength ranges, respectively, to form first and second exposed portions in the first and second light sensitive insulation layers, respectively. The first and second exposed portions are removed by a developing process to form a hole and an opening, respectively. The hole and the opening extend through the first and second light sensitive insulation layers, respectively, to be connected to one another. A conductive layer is formed in the hole and in the opening, and is planarized to form a first via and a second wiring in the hole and in the opening, respectively.

公开(公告)号：US20190214274A1

公开(公告)日：2019-07-11

申请号：US16240220

申请日：2019-01-04

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David AUCHERE

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498 ,  H05K1/11 ,  H01L23/31

CPC classification number: H01L21/486 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49827 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/73103 ,  H05K1/113 ,  H05K2201/09563

Abstract: An insulating spacer provides electrical connection between first contacts of a package for an electronic chip and second contacts of a connector board. The insulating spacer includes conductive vias having rectilinear axes parallel to one another which extend between the first and second contacts. The package for an electronic chip is mounted to one side of the insulating spacer and the connector board is mounted to an opposite side of the insulating spacer.

公开(公告)号：US20190172780A1

公开(公告)日：2019-06-06

申请号：US16266203

申请日：2019-02-04

Applicant: DAI NIPPON PRINTING CO., LTD.

Inventor： Satoru KURAMOCHI ,  Sumio KOIWA ,  Hidenori YOSHIOKA

IPC: H01L23/498 ,  H01L25/18 ,  H05K1/11 ,  H01L23/48 ,  H01L25/065 ,  H05K3/28 ,  H05K3/44

CPC classification number: H01L23/49827 ,  H01L23/13 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/065 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/81805 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/381 ,  H05K1/115 ,  H05K3/28 ,  H05K3/445 ,  H05K2201/09154 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/0959 ,  H05K2201/09854 ,  H05K2203/0594 ,  H01L2924/00014 ,  H01L2924/05432 ,  H01L2924/0665 ,  H01L2924/07025

Abstract: A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

公开(公告)号：US10085354B2

公开(公告)日：2018-09-25

申请号：US15840054

申请日：2017-12-13

Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.

Inventor： Shinya Iizaka

IPC: H05K1/00 ,  H05K3/36 ,  H05K1/14 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K3/363 ,  H05K1/0281 ,  H05K1/113 ,  H05K1/118 ,  H05K1/147 ,  H05K2201/09563

Abstract: A flexible printed circuit (FPC) board having reinforcing pattern against bending is disclosed. The FPC board provides an RF interconnection extending from an RF electrode. Two ground electrodes are formed in respective sides of the RF electrode. The ground electrodes extend respective extended portions along the RF interconnection to protect the RF interconnection from breakage due to bending of the FPC board. The extended portion provides an end portion bent toward the RF interconnection to compensate for impedance mismatching of the RF interconnection.

公开(公告)号：US10080295B2

公开(公告)日：2018-09-18

申请号：US13667651

申请日：2012-11-02

Applicant: Unimicron Technology Corporation

Inventor： Kun-Chen Tsai

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/20 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/205 ,  H01L2924/0002 ,  H05K3/423 ,  H05K3/465 ,  H05K3/4682 ,  H05K2201/09563 ,  H05K2201/09881 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Provided are a circuit board structure and a fabrication method thereof, including the steps of: forming a first circuit layer in a first dielectric layer and exposing the first circuit layer therefrom; forming a second dielectric layer on the first dielectric layer and the first circuit layer, and forming a second circuit layer on the second dielectric layer; forming a plurality of first conductive vias in the second dielectric layer for electrically connecting to the first circuit layer to thereby dispense with a core board and electroplated holes and thus facilitate miniaturization. Further, the first dielectric layer is liquid before being hardened and is formed on the first dielectric layer that enhances the bonding between layers of the circuit board and the structure.

公开(公告)号：US20180254238A1

公开(公告)日：2018-09-06

申请号：US15699810

申请日：2017-09-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li Chuan TSAI ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H01L21/48 ,  H05K3/34 ,  H05K1/11

CPC classification number: H01L23/49811 ,  H01L21/4832 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/113 ,  H05K3/3452 ,  H05K2201/09563 ,  H01L2924/00012 ,  H01L2224/13099

Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device. The substrate includes a first dielectric layer having a first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a conductive post. The first patterned conductive layer includes a first conductive pad and a second conductive pad. The conductive post is disposed on the first conductive pad. The conductive post includes a first portion and a second portion. The first portion and the second portion of the conductive post are exposed by the first dielectric layer. The first portion of the conductive post has a first width corresponding to a top line width of the first portion and the second portion of the conductive post has a width. The width of the second portion of the conductive post is greater than the first width of the first portion of the conductive post.