WIRING BOARD AND MANUFACTURING METHOD THEREFOR

    公开(公告)号:US20240357739A1

    公开(公告)日:2024-10-24

    申请号:US18639407

    申请日:2024-04-18

    发明人: Tomoyuki Ishii

    IPC分类号: H05K1/03 H05K3/00 H05K3/46

    摘要: A wiring board includes: a substrate; a first seed layer provided on the substrate; a first conductive layer provided on the first seed layer; a first insulating layer provided on the first conductive layer; a second seed layer provided on the first insulating layer; and a second conductive layer provided on the second seed layer. An area of the first insulating layer is smaller than an area of the first conductive layer. An area of the second conductive layer is smaller than the area of the first insulating layer. A region of the first insulating layer not overlapping the second conductive layer includes a first region surrounding the second conductive layer and a second region outside the first region. A surface roughness of the second region is larger than a surface roughness of the first region.

    CIRCUIT BOARD
    3.
    发明公开
    CIRCUIT BOARD 审中-公开

    公开(公告)号:US20240349420A1

    公开(公告)日:2024-10-17

    申请号:US18613894

    申请日:2024-03-22

    IPC分类号: H05K1/02 H05K1/03

    CPC分类号: H05K1/028 H05K1/0386

    摘要: A circuit board includes a base material portion having a sheet-like shape, an electric circuit pattern portion being formed on at least one of surfaces of the base material portion and being conductive, a folding portion where a linear fold is to be formed to divide, when the circuit board is bent, each of the base material portion and the electric circuit pattern portion into a first area and a second area, and a disconnection preventing portion that prevents disconnection between the first area and the second area in the electric circuit pattern portion in a state where the circuit board is bent at the folding portion.

    WIRING SUBSTRATE
    7.
    发明公开
    WIRING SUBSTRATE 审中-公开

    公开(公告)号:US20240334598A1

    公开(公告)日:2024-10-03

    申请号:US18614865

    申请日:2024-03-25

    摘要: A wiring substrate includes a first wiring layer, an insulation layer covering a side surface of the first wiring layer and exposing part of the first wiring layer, and a second wiring layer formed on the first wiring layer exposed from the insulation layer. The insulation layer includes a resin and a filler. The insulation layer includes an upper surface having a structure in which the filler is exposed from the resin. The second wiring layer includes a first metal film, covering the upper surface of the insulation layer and the wiring layer exposed from the insulation layer, and a metal layer, formed above the first metal film. The first metal film is formed from a CuNiTi alloy and has a Ni content rate of 5 wt % or greater and 30 wt % or less and a Ti content rate of 5 wt % or greater and 15 wt % or less.