公开(公告)号：US12125715B2

公开(公告)日：2024-10-22

申请号：US18341052

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Ching Hsu ,  Yu-Huan Chen ,  Chen-Shien Chen

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/4853 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16227 ,  H01L2224/81035 ,  H01L2224/81047 ,  H01L2224/81192 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81493

Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate including a substrate, a first pad, and a second pad. The first pad and the second pad are respectively over a first surface and a second surface of the substrate, and the first pad is narrower than the second pad. The chip package structure includes a nickel layer over the first pad. The nickel layer has a T-shape in a cross-sectional view of the nickel layer. The chip package structure includes a chip over the wiring substrate. The chip package structure includes a conductive bump between the nickel layer and the chip.

公开(公告)号：US20240339381A1

公开(公告)日：2024-10-10

申请号：US18130582

申请日：2023-04-04

Applicant: Intel Corporation

Inventor： Hiroki TANAKA ,  Veronica STRONG ,  Henning BRAUNISCH ,  Haobo CHEN ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Brandon C. MARIN

IPC: H01L23/482 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L23/4821 ,  H01L21/76831 ,  H01L23/49827 ,  H01L23/49866 ,  H01L21/30604 ,  H05K2201/09218

Abstract: Embodiments disclosed herein include an interposer. In an embodiment, the interposer comprises a substrate, where the substrate comprises a glass layer. In an embodiment, a trace is on the substrate, where the trace has a bottom surface, sidewall surfaces, and a top surface. In an embodiment, the sidewall surfaces and the top surface are exposed to air. In an embodiment, a trench into the substrate is adjacent to at least one sidewall surface of the trace.

公开(公告)号：US20240332153A1

公开(公告)日：2024-10-03

申请号：US18129880

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Tchefor NDUKUM ,  Yonggang LI ,  Rengarajan SHANMUGAM ,  Darko GRUJICIC ,  Deniz TURAN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49866

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate and a seed layer over the substrate. In an embodiment, sidewalls of the seed layer are sloped. In an embodiment, the electronic package further comprises a feature over the seed layer, where the feature is electrically conductive.

公开(公告)号：US12100647B2

公开(公告)日：2024-09-24

申请号：US17765365

申请日：2020-09-30

Applicant: SAMTEC, INC.

Inventor： Alan D. Nolet ,  Andrew Haynes Liotta ,  Troy Benton Holland ,  Thomas Jacob Hammann ,  Heidi Bates ,  Daniel Goia ,  Vishwas Vinayak Hardikar ,  Ajeet Kumar ,  Daniel Long ,  Nicole McGraw ,  Lauren Savawn Moen ,  Adam Owens

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11

CPC classification number: H01L23/49866 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827 ,  H05K1/0306 ,  H05K1/115

Abstract: An electrical component is provided by metallizing holes that extend through a glass substrate. The electrical component can be fabricated by forcing a suspension of electrically conductive particles suspended in a liquid medium through the holes. The suspension can be forced into the holes under an air pressure differential such as a pressure differential force, a centrifugal force, or an electrostatic force. The liquid medium in the holes can be dried, and the particles can be sintered. The particles can further be packed in the hole. Alternatively or additionally, the particles can be pressed against the outer surfaces of the substrate to produce buttons.

公开(公告)号：US20240312865A1

公开(公告)日：2024-09-19

申请号：US18182879

申请日：2023-03-13

Applicant: Intel Corporation

Inventor： Kyle Arrington ,  Bohan Shan ,  Haobo Chen ,  Bai Nie ,  Srinivas Pietambaram ,  Gang Duan ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/3733 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/49877 ,  H01L23/15

Abstract: Methods, systems, apparatus, and articles of manufacture to improve reliability of vias in a glass substrate of an integrated circuit package are disclosed. An example integrated circuit (IC) package substrate includes a glass substrate, a via extending between first and second surfaces of the glass substrate, and a conductive material provided in the via, the conductive material including gallium and silver.

公开(公告)号：US20240258243A1

公开(公告)日：2024-08-01

申请号：US18614579

申请日：2024-03-22

Applicant: Micron Technology, Inc.

Inventor： Jong Sik Paek

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/5386 ,  H01L21/4846 ,  H01L21/566 ,  H01L21/76871 ,  H01L21/76879 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/32 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48228 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2924/1436 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/183

Abstract: Stacked die modules for semiconductor device assemblies and methods of manufacturing the modules are disclosed. In some embodiments, the module includes a shingled stack of semiconductor dies, each die having an uncovered porch with bond pads. Further, a dielectric structure partially encapsulates the shingled stack of semiconductor dies. The dielectric structure includes openings corresponding to the bond pads. The module also includes conductive structures disposed on the dielectric structure, where each of the conductive structures extends over at least one porch of the semiconductor dies to connect to at least one bond pad through a corresponding opening. The semiconductor device assembly may include a controller die attached to a package substrate, the controller die carrying one or more stacked die modules, and bonding wires connecting terminals of the modules to package bond pads.

公开(公告)号：US20240234280A1

公开(公告)日：2024-07-11

申请号：US18611641

申请日：2024-03-20

Applicant: TOPPAN HOLDINGS INC.

Inventor： Ryo WARIGAYA ,  Ryoma TANABE ,  Masahito TANABE

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A substrate including a support and a wiring board provided on the support, the wiring board includes an insulating film on the inside thereof configured by a first organic insulating resin; the wiring board has a first surface and a second surface each provided with electrodes that can be connected to a semiconductor element and the like; at least one of an upper surface layer and a lower surface layer of the wiring board is provided with an insulating film configured by a second organic insulating resin; and the second organic insulating resin has a CTE lower than that of the first organic insulating resin.

公开(公告)号：US20240222280A1

公开(公告)日：2024-07-04

申请号：US18363995

申请日：2023-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： MyungDo CHO ,  Youngchan KO ,  Gyeongho KIM ,  Byung Ho KIM ,  Yongkoon LEE ,  Jeongho LEE

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/49866 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/182

Abstract: A semiconductor package may include: a first redistribution layer structure; a bridge structure on the first redistribution layer structure; a plurality of conductive pillars on the first redistribution layer structure and side by side with the bridge structure; an encapsulant molding the bridge structure and the plurality of conductive pillars on the first redistribution layer structure; a second redistribution layer structure on the encapsulant, wherein a region of the second redistribution layer structure on the bridge structure is defined as a first region and a region other than the first region is defined as a second region; and a plurality of bonding pads at the first region. A vertical thickness of the first region may be smaller than a vertical thickness of the second region.

公开(公告)号：US12009320B2

公开(公告)日：2024-06-11

申请号：US16596383

申请日：2019-10-08

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Cemil Geyik ,  Jiwei Sun ,  Gang Duan ,  Kemal Aygün

IPC: H01L23/49 ,  H01L23/498 ,  H01L23/64

CPC classification number: H01L23/645 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866

Abstract: Embodiments include package substrates and a semiconductor package with such package substrates. A package substrate includes a first conductive layer in a first magnetic layer, and a second magnetic layer over the first magnetic layer, where the first and second magnetic layers include magnetic materials. The package substrate also includes a second conductive layer in the second magnetic layer. The second conductive layer includes a plurality of first traces fully surrounded by the first and second magnetic layers. The package substrate includes a third conductive layer over the second magnetic layer. The magnetic materials may include manganese Mn ferrite materials, Zn/Mn ferrite materials, or Ni/Zn ferrite materials. The magnetic materials include material properties with a low constant value, a magnetic tangent value, a frequency, a base filler chemistry, a filler shape, a filler orientation, a filler percentage, a loading fraction value, a permeability, an insertion loss, and a resin formulation.

公开(公告)号：US20240107682A1

公开(公告)日：2024-03-28

申请号：US18304500

申请日：2023-04-21

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Chao-Wei Chiu ,  Chih-Chiang Tsao ,  Jen-Jui Yu ,  Hsuan-Ting Kuo ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC: H05K3/34 ,  B23K35/02 ,  B23K35/26 ,  C22C13/00 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01R4/02 ,  H01R4/62 ,  H05K1/18 ,  H10B80/00

CPC classification number: H05K3/3463 ,  B23K35/0244 ,  B23K35/262 ,  C22C13/00 ,  H01L23/49816 ,  H01L23/49866 ,  H01L23/562 ,  H01L25/18 ,  H01R4/02 ,  H01R4/625 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/3494 ,  H10B80/00 ,  H01L23/5385

Abstract: An embodiment composite material for semiconductor package mount applications may include a first component including a tin-silver-copper alloy and a second component including a tin-bismuth alloy or a tin-indium alloy. The composite material may form a reflowed bonding material having a room temperature tensile strength in a range from 80 MPa to 100 MPa when subjected to a reflow process. The reflowed bonding material may include a weight fraction of bismuth that is in a range from approximately 4% to approximately 15%. The reflowed bonding material may an alloy that is solid solution strengthened by a presence of bismuth or indium that is dissolved within the reflowed bonding material or a solid solution phase that includes a minor component of bismuth dissolved within a major component of tin. In some embodiments, the reflowed bonding material may include intermetallic compounds formed as precipitates such as Ag3Sn and/or Cu6Sn5.