公开(公告)号：US20230294204A1

公开(公告)日：2023-09-21

申请号：US17698024

申请日：2022-03-18

申请人： Intel Corporation

发明人： Jeremy ECTON ,  Vinith BEJUGAM ,  Jefferson KAPLAN ,  Yonggang LI ,  Whitney BRYKS ,  Samuel GEORGE ,  Jeremy CROSS

IPC分类号： B23K26/142 ,  B23K26/08 ,  B08B3/08

CPC分类号： B23K26/142 ,  B23K26/0823 ,  B08B3/08

摘要： A method includes forming a solvent on a stage, and placing, on the solvent formed on the stage, a bottom surface of a substrate on which a residue is formed, so that the residue moves away from the bottom surface of the substrate into the solvent. The method further includes removing the substrate from the solvent into which the residue is moved.

公开(公告)号：US20210305668A1

公开(公告)日：2021-09-30

申请号：US17344715

申请日：2021-06-10

申请人： Intel Corporation

发明人： Brandon C. MARIN ,  Jeremy D. ECTON ,  Aleksandar ALEKSOV ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Dilan SENEVIRATNE

IPC分类号： H01P1/208 ,  H01L23/66 ,  H01P7/10 ,  H01P3/16 ,  H01L21/768 ,  H01P11/00 ,  H01L21/288 ,  H01P1/20

摘要： A method of fabricating an RF filter on a semiconductor package comprises forming a first dielectric buildup film. A second dielectric buildup film is formed over the first dielectric buildup film, the second dielectric buildup film comprising a dielectric material that contains a metallization catalyst, wherein the dielectric material comprises one of an epoxy-polymer blend dielectric material, silicon dioxide and silicon nitride, and a low-k dielectric. A trench is formed in the second dielectric buildup film with laser ablation, wherein the laser ablation selectively activates sidewalls of the trench for electroless metal deposition. A metal selectively is plated to sidewalls of the trench based at least in part on the metallization catalyst and immersion in an electroless solution. A low-loss buildup film is formed over the metal that substantially fills the trench.

公开(公告)号：US20200312771A1

公开(公告)日：2020-10-01

申请号：US16366661

申请日：2019-03-27

申请人： Intel Corporation

发明人： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

摘要： A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20200083164A1

公开(公告)日：2020-03-12

申请号：US16129711

申请日：2018-09-12

申请人： Intel Corporation

发明人： Brandon C. MARIN ,  Frank TRUONG ,  Shivasubramanian BALASUBRAMANIAN ,  Dilan SENEVIRATNE ,  Yonggang LI ,  Sameer PAITAL ,  Darko GRUJICIC ,  Rengarajan SHANMUGAM ,  Melissa WETTE ,  Srinivas PIETAMBARAM

IPC分类号： H01L23/522 ,  H01L49/02 ,  H01L27/01 ,  H01L21/768 ,  H01L23/00

摘要： Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.

公开(公告)号：US20240332153A1

公开(公告)日：2024-10-03

申请号：US18129880

申请日：2023-04-02

申请人： Intel Corporation

发明人： Tchefor NDUKUM ,  Yonggang LI ,  Rengarajan SHANMUGAM ,  Darko GRUJICIC ,  Deniz TURAN

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC分类号： H01L23/49838 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49866

摘要： Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate and a seed layer over the substrate. In an embodiment, sidewalls of the seed layer are sloped. In an embodiment, the electronic package further comprises a feature over the seed layer, where the feature is electrically conductive.

公开(公告)号：US20240213328A1

公开(公告)日：2024-06-27

申请号：US18089494

申请日：2022-12-27

申请人： INTEL CORPORATION

发明人： Vinith BEJUGAM ,  Yonggang LI ,  Srinivas V. PIETAMBARAM ,  Chandrasekharan NAIR ,  Whitney BRYKS ,  Gene CORYELL

IPC分类号： H01L29/16 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC分类号： H01L29/1606 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/16 ,  H01L2924/15311

摘要： Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core with a via opening through the core. In an embodiment, the via opening comprises sidewalls. In an embodiment, a composite layer is provided along the sidewalls, and the composite layer comprises carbon. In an embodiment, the package substrate further comprises a via within the via opening, where the via is electrically conductive.

公开(公告)号：US20240096678A1

公开(公告)日：2024-03-21

申请号：US17949258

申请日：2022-09-21

申请人： Intel Corporation

发明人： Deniz TURAN ,  Yosef KORNBLUTH ,  Yonggang LI

IPC分类号： H01L21/683 ,  H01L21/677

CPC分类号： H01L21/6833 ,  H01L21/67781

摘要： The present disclosure is directed to a carrier chuck having a base plate with a top surface, at least one electrode positioned in a first carrier region of the top surface and configured to produce an electrostatic force to retain a panel placed on the carrier chuck during panel processing, and a dielectric layer positioned over the at least one electrode. The at least one electrode extends from the top surface by a height of at least 20 um.

公开(公告)号：US20240181572A1

公开(公告)日：2024-06-06

申请号：US18060578

申请日：2022-12-01

申请人： Intel Corporation

发明人： Tchefor NDUKUM ,  Deniz TURAN ,  Yonggang LI

IPC分类号： B23K26/40 ,  B23K26/0622 ,  B23K26/082

CPC分类号： B23K26/40 ,  B23K26/0622 ,  B23K26/082 ,  B23K2101/40

摘要： The present disclosure generally relates to a method. The method may include providing a substrate and forming a seed layer on the substrate. The method may further include forming a first metal layer on selected portions of the seed layer to form exposed portions of the seed layer. The method may also include scanning a laser beam across the substrate to remove the exposed portions of the seed layer to form exposed portions of the substrate.

公开(公告)号：US20240088052A1

公开(公告)日：2024-03-14

申请号：US18513015

申请日：2023-11-17

申请人： Intel Corporation

发明人： Bai NIE ,  Gang DUAN ,  Srinivas PIETAMBARAM ,  Jesse JONES ,  Yosuke KANAOKA ,  Hongxia FENG ,  Dingying XU ,  Rahul MANEPALLI ,  Sameer PAITAL ,  Kristof DARMAWIKARTA ,  Yonggang LI ,  Meizi JIAO ,  Chong ZHANG ,  Matthew TINGEY ,  Jung Kyu HAN ,  Haobo CHEN

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/381

摘要： A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20230146165A1

公开(公告)日：2023-05-11

申请号：US18091989

申请日：2022-12-30

申请人： Intel Corporation

发明人： Srinivas PIETAMBARAM ,  Kristof DARMAWIKARTA ,  Gang DUAN ,  Yonggang LI ,  Sameer PAITAL

IPC分类号： H01F27/26 ,  H01F27/42 ,  H01L21/768 ,  H01L23/64

CPC分类号： H01F27/26 ,  H01F27/425 ,  H01L21/76871 ,  H01L23/645 ,  H01F27/25

摘要： Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.