Patent search cpc:"H01L2924/381" Page 1

1.

发明授权
High density interconnect device and method 有权

公开(公告)号：US12094831B2

公开(公告)日：2024-09-17

申请号：US18301700

申请日：2023-04-17

Applicant: Tahoe Research, Ltd.

Inventor： Mihir K. Roy , Mathew J. Manusharow

IPC: H01L23/538 , H01L21/48 , H01L23/00 , H01L23/13 , H01L23/14 , H01L25/00 , H01L25/065 , H01L25/18

CPC classification number: H01L23/5386 , H01L21/4853 , H01L21/4857 , H01L23/13 , H01L23/5381 , H01L23/5383 , H01L23/5385 , H01L24/14 , H01L24/17 , H01L24/25 , H01L24/81 , H01L25/0655 , H01L25/18 , H01L25/50 , H01L23/147 , H01L24/13 , H01L2224/13101 , H01L2224/1412 , H01L2224/14505 , H01L2224/16225 , H01L2224/16238 , H01L2224/1712 , H01L2224/24146 , H01L2224/2541 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2224/81986 , H01L2924/12042 , H01L2924/1432 , H01L2924/14335 , H01L2924/1434 , H01L2924/15153 , H01L2924/15747 , H01L2924/381 , H01L2224/13101 , H01L2924/014 , H01L2924/00014 , H01L2224/81815 , H01L2924/00014 , H01L2224/81203 , H01L2924/00014 , H01L2224/81986 , H01L2224/81815 , H01L2924/12042 , H01L2924/00

Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via. Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

2.

发明公开
INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 审中-公开

公开(公告)号：US20240234254A9

公开(公告)日：2024-07-11

申请号：US18456865

申请日：2023-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongwee YU , Junho HUH

IPC: H01L23/48 , H01L23/00 , H01L23/498 , H01L25/065

CPC classification number: H01L23/481 , H01L23/49827 , H01L23/49838 , H01L24/16 , H01L25/0657 , H01L2224/16225 , H01L2225/06541 , H01L2924/381

Abstract: An integrated circuit device including a first semiconductor chip, a plurality of signal through silicon vias (TSV), a second semiconductor chip, a plurality of signal bumps and an interposer may be provided. The signal TSVs may be in the first semiconductor chip by a first pitch. The second semiconductor chip may be on the first semiconductor chip. The signal bumps may be on a lower surface of the second semiconductor chip by a second pitch wider than the first pitch. The interposer may be interposed between the first semiconductor chip and the second semiconductor chip and may be electrically connecting the signal TSVs with the signal bumps. Thus, an occupying area of the signal TSVs in the first semiconductor chip may be decreased so that the integrated circuit device may have a smaller size.

3.

发明公开
OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-ON- PACKAGE STRUCTURES 审中-公开

公开(公告)号：US20240222350A1

公开(公告)日：2024-07-04

申请号：US18610104

申请日：2024-03-19

Applicant: Intel Corporation

Inventor： Russell K. MORTENSEN , Robert M. NICKERSON , Nicholas R. WATTS

IPC: H01L25/18 , H01L21/48 , H01L23/00 , H01L23/498 , H01L25/00 , H01L25/065 , H01L25/10 , H05K1/11 , H05K3/40

CPC classification number: H01L25/18 , H01L21/4846 , H01L23/49816 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L24/03 , H01L24/09 , H01L24/11 , H01L24/17 , H01L24/43 , H01L24/49 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/89 , H01L25/0657 , H01L25/105 , H01L25/50 , H05K1/113 , H05K3/4038 , H01L24/16 , H01L24/32 , H01L24/48 , H01L2224/0401 , H01L2224/0557 , H01L2224/08238 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/48245 , H01L2224/48472 , H01L2224/73204 , H01L2224/73257 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2225/1023 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/143 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L2924/1511 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/381 , Y10T29/49124

Abstract: An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

4.

发明公开
SYSTEM-LEVEL FAN-OUT PACKAGING STRUCTURE AND METHOD FOR MANUFACTURING SAME 审中-公开

公开(公告)号：US20240088002A1

公开(公告)日：2024-03-14

申请号：US18244315

申请日：2023-09-11

Applicant: SJ Semiconductor(Jiangyin) Corporation

Inventor： Yenheng CHEN , Chengchung LIN

IPC: H01L23/498 , H01L21/48 , H01L21/56 , H01L21/683 , H01L23/00 , H01L23/29 , H01L25/065

CPC classification number: H01L23/49822 , H01L21/4853 , H01L21/4857 , H01L21/568 , H01L21/6835 , H01L23/293 , H01L23/49811 , H01L23/49838 , H01L23/49894 , H01L24/03 , H01L24/08 , H01L24/80 , H01L25/0655 , H01L2221/68359 , H01L2221/68372 , H01L2221/68381 , H01L2224/03916 , H01L2224/08225 , H01L2224/80895 , H01L2224/80896 , H01L2924/15174 , H01L2924/3511 , H01L2924/3512 , H01L2924/381

Abstract: A system-level fan-out packaging structure and a method for manufacturing the same are disclosed. The method includes: forming a rewiring layer on a supporting substrate, the rewiring layer having a first surface and a second surface opposite to the first surface, wherein the rewiring layer includes at least one inorganic dielectric layer and at least one metal wiring layer; forming a hybrid bonding structure between the first surface of the rewiring layer and semiconductor chips to electrically couple them, wherein the hybrid bonding structure includes a first bonding layer formed on the first surface of the rewiring layer; a plastic packaging layer on the first surface of the rewiring layer to cover the semiconductor chips; removing the supporting substrate to expose the second surface of the rewiring layer; and providing a packaging substrate electrically coupled to the second surface of the rewiring layer.

5.

发明公开
PARTITIONING WAFER PROCESSING AND HYBRID BONDING OF LAYERS FORMED ON DIFFERENT WAFERS FOR A SEMICONDUCTOR ASSEMBLY 审中-公开

公开(公告)号：US20240071985A1

公开(公告)日：2024-02-29

申请号：US17896746

申请日：2022-08-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RAHUL AGARWAL , CHANDRA SEKHAR MANDALAPU , RAJA SWAMINATHAN

IPC: H01L23/00 , H01L25/065

CPC classification number: H01L24/80 , H01L24/08 , H01L25/0657 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2225/06524 , H01L2225/06527 , H01L2924/381

Abstract: A method for forming a semiconductor assembly that includes forming a first set of layers on a first wafer, where one or more layers of the first set includes one or more devices of the semiconductor assembly. The method further includes forming a second set of layers on a second wafer, where one or more layers of the second set include connections between one or more of the devices of the semiconductor assembly. The method additionally includes coupling a layer of the first set to a layer of the second set using metal to metal hybrid bonding.

6.

发明公开
CAVITY-LESS INTERCONNECT COMPONENT ON GLASS CORE 审中-公开

公开(公告)号：US20240071938A1

公开(公告)日：2024-02-29

申请号：US17900692

申请日：2022-08-31

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton , Hiroki Tanaka , Brandon Christian Marin , Srinivas V. Pietambaram , Suddhasattwa Nad

IPC: H01L23/538 , H01L21/48 , H01L23/00 , H01L23/15 , H01L23/498 , H01L25/065

CPC classification number: H01L23/5381 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L23/15 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L23/5385 , H01L23/5386 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/0655 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/37001 , H01L2924/381

Abstract: A glass core with a cavity-less local interconnect component architecture for complex multi-die packages. The apparatus has the local interconnect component attached directly to a planar glass layer and surrounded by mold. One or more redistribution layers may be located above and below the apparatus.

7.

发明公开
THREE DIMENSIONAL UNIVERSAL CHIPLET INTERCONNECT AS ON-PACKAGE INTERCONNECT 审中-公开

公开(公告)号：US20240030172A1

公开(公告)日：2024-01-25

申请号：US18479014

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Debendra Das Sharma , Peter Z. Onufryk , Gerald S. Pasdast , Sathya Narasimman Tiagaraj

IPC: H01L23/00 , H01L25/065

CPC classification number: H01L24/16 , H01L25/0657 , H01L2225/06513 , H01L2224/16145 , H01L2924/1431 , H01L2924/381

Abstract: Methods and apparatus relating to a Universal Chiplet Interconnect Express™ (UCIe™)-Three Dimensional (UCIe-3D™) interconnect which may be utilized as an on-package interconnect are described. In one embodiment, an interconnect communicatively couples a first physical layer module of a first chiplet on a semiconductor package to a second physical layer module of a second chiplet on the semiconductor package. A first Network-on-chip Controller (NoC) logic circuitry controls the first physical layer module. A second NoC logic circuitry controls the second physical layer module. Other embodiments are also claimed and disclosed.

8.

发明公开
SEMICONDUCTOR PACKAGE 审中-公开

公开(公告)号：US20230411268A1

公开(公告)日：2023-12-21

申请号：US18138180

申请日：2023-04-24

Applicant: LG INNOTEK CO., LTD.

Inventor： Hodol YOO , Seongun EOM , Yongsoo LEE

IPC: H01L23/498 , H01L23/00 , H01L25/10 , H01L25/065 , H10B80/00

CPC classification number: H01L23/49838 , H01L24/16 , H01L24/32 , H01L24/73 , H01L25/105 , H01L25/0657 , H01L23/49816 , H01L23/49822 , H01L23/49833 , H10B80/00 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06548 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2224/16148 , H01L2224/16227 , H01L2224/16238 , H01L2224/32225 , H01L2224/73204 , H01L2924/3841 , H01L2924/381 , H01L2224/10175 , H01L2924/1434 , H01L2924/1431

Abstract: A semiconductor package substrate including a substrate; a first protective layer disposed on the substrate and including a through hole; and a second protective layer disposed inside the through hole of the first protective layer and spaced apart from the first protective layer, wherein a first edge of the first protective layer faces a first edge of the second protective layer, wherein a space between the first edge of the first protective layer and the first edge of the second protective layer includes at least a first separation region and a second separation region, and wherein a first width of the space in the first separation region is different than a second width of the space in the second separation region.