公开(公告)号：US12133008B2

公开(公告)日：2024-10-29

申请号：US17798460

申请日：2021-01-26

Applicant: Sony Semiconductor Solutions Corporation

Inventor： Satoshi Azuhata

IPC: H04N25/75 ,  H04N25/768 ,  H04N25/772 ,  H04N25/778 ,  H04N25/79

CPC classification number: H04N25/75 ,  H04N25/768 ,  H04N25/772 ,  H04N25/778 ,  H04N25/79

Abstract: To improve a frame rate in a solid-state imaging element that compares a reference signal and a pixel signal.
The solid-state imaging element includes a differential amplifier circuit, a transfer transistor, and a source follower circuit. The differential amplifier circuit amplifies a difference between the potentials of a pair of input nodes and outputs the difference from an output node. The transfer transistor transfers charge from a photoelectric conversion element to a floating diffusion layer. The auto-zero transistor short-circuits the floating diffusion layer and the output node in a predetermined period. The source follower circuit supplies a potential to one of the pair of input nodes according to a potential of the floating diffusion layer.

公开(公告)号：US12120449B2

公开(公告)日：2024-10-15

申请号：US17423810

申请日：2020-01-08

Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Inventor： Luonghung Asakura

IPC: H04N25/79 ,  H01L23/00 ,  H01L27/146 ,  H04N25/40 ,  H04N25/75 ,  H04N25/77

CPC classification number: H04N25/79 ,  H01L24/08 ,  H01L27/14634 ,  H01L27/14636 ,  H04N25/40 ,  H04N25/75 ,  H04N25/77 ,  H01L2224/08145

Abstract: An image capturing device of the present disclosure has a stacked chip structure in which at least two semiconductor chips including a first semiconductor chip and a second semiconductor chip are stacked. Pixels each including a light receiving portion are arranged on the first semiconductor chip, and a scanning section that selectively scans the pixel and a signal processing section that processes an analog signal output from the pixel are arranged on the second semiconductor chip. Further, the scanning section is arranged along pixel rows of the pixel arrangement in the matrix form.

公开(公告)号：US20240340551A1

公开(公告)日：2024-10-10

申请号：US18746479

申请日：2024-06-18

Applicant: Sony Semiconductor Solutions Corporation

Inventor： Luonghung Asakura ,  Yoshiaki Inada

IPC: H04N25/77 ,  H04N25/616 ,  H04N25/65 ,  H04N25/78 ,  H04N25/79

CPC classification number: H04N25/77 ,  H04N25/616 ,  H04N25/65 ,  H04N25/78 ,  H04N25/79

Abstract: Solid-state imaging elements are disclosed. In one example, an upstream circuit sequentially generates a predetermined reset level and a signal level corresponding to an exposure amount, and causes first and second capacitive elements to hold the reset level and the signal level. A selection circuit sequentially connects one of the capacitive elements to a predetermined downstream node, disconnects both capacitive elements from the downstream node, and connects the other capacitive element to the downstream node. A downstream reset transistor initializes a level of the downstream node when both capacitive elements are disconnected from the downstream node. A downstream circuit sequentially reads the reset level and the signal level from the first and second capacitive elements via the downstream node and outputs the reset level and the signal level.

公开(公告)号：US12114091B2

公开(公告)日：2024-10-08

申请号：US18002798

申请日：2021-06-24

Applicant: Beijing RuisiZhixin Technology Co., Ltd. ,  Alpsentek GmbH

Inventor： Yingyun Zha ,  Roger Mark Bostock ,  Jian Deng ,  Yu Zou

IPC: H04N25/771 ,  G06F7/02 ,  H03M1/12 ,  H04N25/40 ,  H04N25/47 ,  H04N25/703 ,  H04N25/766 ,  H04N25/772 ,  H04N25/78 ,  H04N25/79

CPC classification number: H04N25/771 ,  G06F7/02 ,  H03M1/12 ,  H04N25/40 ,  H04N25/47 ,  H04N25/703 ,  H04N25/766 ,  H04N25/772 ,  H04N25/78 ,  H04N25/79

Abstract: A delta image sensor comprising a plurality of acquisition circuits corresponding to at least one pixel. Each acquisition circuit includes at least one sensor circuit comprising a photosensor to generate a sensor signal, VSIG, depending on a light signal illuminating the photosensor; at least one single slope analogue to digital conversion, A/D, circuit configured to convert a current VSIG to a digital signal, wherein the A/D circuit (12) is configured to use one of a plurality of ramps for the conversion; at least one digital storage circuit configured to store a representation of at least one digital signal corresponding to a previous VSIG; at least one digital comparison circuit configured to compare the level of the stored representation with the current VSIG to detect whether a changed level is present; and at least one digital output circuit configured to generate an event output, in response to the changed level.

公开(公告)号：US20240305899A1

公开(公告)日：2024-09-12

申请号：US18456017

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho KIM ,  Jae-Heung LIM ,  Gihoan CHO ,  Sunyong LEE

IPC: H04N23/80 ,  H04N23/667 ,  H04N25/79

CPC classification number: H04N23/80 ,  H04N23/667 ,  H04N25/79

Abstract: An image sensor includes a pixel array including pixels, an image data generation circuit configured to generate first image data based on signals of the pixels and output the first image data, and an image data translation circuit configured to generate second image data based on translating the first image data and outputting the second image data to an external host device. The image data generation circuit has a vertical blank interval and a frame interval alternately, is configured to not output the first image data during the vertical blank interval, and is configured to output one frame of the first image data during the frame interval. The image data translation circuit is configured to perform a preparation operation to translate a frame of the first image data into a frame of the second image data in a next frame interval, during the vertical blank interval.

公开(公告)号：US20240305895A1

公开(公告)日：2024-09-12

申请号：US18664980

申请日：2024-05-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： HIROAKI IIJIMA ,  MASASHI MURAKAMI

IPC: H04N23/73 ,  H04N25/10 ,  H04N25/532 ,  H04N25/79

CPC classification number: H04N23/73 ,  H04N25/10 ,  H04N25/532 ,  H04N25/79

Abstract: An imaging device includes a first pixel and a second pixel. The first pixel includes a first photoelectric converter that generates first signal charge by photoelectric conversion and that has sensitivity to a first wavelength range that is invisible and a first signal detection circuit connected to the first photoelectric converter. The second pixel includes a second photoelectric converter that generates second signal charge by photoelectric conversion and that has sensitivity to a second wavelength range and a second signal detection circuit connected to the second photoelectric converter. An exposure period of the second photoelectric converter does not overlap a light-emitting period of light based on lighting, the light being incident on the first photoelectric converter and having a luminescence peak in the first wavelength range. A readout period during which the second signal detection circuit reads out the second signal charge does not overlap the light-emitting period.

公开(公告)号：US20240292123A1

公开(公告)日：2024-08-29

申请号：US18572749

申请日：2022-06-29

Applicant: VoxelSensors SRL

Inventor： Ward VAN DER TEMPEL ,  Johannes Willem PEETERS ,  André Bernard MIODEZKY, ,  Christian MOURAD

IPC: H04N25/60 ,  H04N23/71 ,  H04N25/77 ,  H04N25/79

CPC classification number: H04N25/60 ,  H04N23/71 ,  H04N25/77 ,  H04N25/79

Abstract: The present invention relates to an improved system and method for imaging, based on single photon detectors (SPDs), whereby false positives are suppressed.

公开(公告)号：US20240290811A1

公开(公告)日：2024-08-29

申请号：US18346530

申请日：2023-07-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Hsien Chung ,  Tzu-Jui Wang ,  Chia-Chi Hsiao ,  Chen-Jong Wang ,  Dun-Nian Yaung

IPC: H01L27/146 ,  H04N25/79

CPC classification number: H01L27/14634 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/1469 ,  H04N25/79

Abstract: The present disclosure relates to an image sensor integrated chip structure. The image sensor integrated chip structure includes one or more logic devices disposed within a first substrate and coupled to a first interconnect structure on the first substrate. A plurality of pixel support devices are disposed along a first-side of a second substrate and coupled to a second interconnect structure on the second substrate. The first substrate is bonded to the second substrate. A plurality of image sensing elements are disposed within a third substrate in pixel regions respectively including two or more of the plurality of image sensing elements. A plurality of transfer gates and a third interconnect structure are disposed on a first-side of the third substrate. The third interconnect structure includes interconnect wires and vias confined between the first-side of second substrate and the first-side of the third substrate.

公开(公告)号：US12075180B2

公开(公告)日：2024-08-27

申请号：US17827513

申请日：2022-05-27

Applicant: Gigajot Technology, Inc.

Inventor： Jiaju Ma ,  Donald Hondongwa

IPC: H04N25/778 ,  H01L27/146 ,  H04N25/53 ,  H04N25/709 ,  H04N25/75 ,  H04N25/79

CPC classification number: H04N25/778 ,  H01L27/14612 ,  H04N25/53 ,  H04N25/709 ,  H04N25/75 ,  H04N25/79

Abstract: An amplifier transistor within an image-sensor pixel is implemented upside down relative to conventional orientation such that a substrate-resident floating diffusion node of the pixel forms the gate of the amplifier transistor—achieving increased pixel conversion gain by eliminating the conventional metal-layer interconnection between the floating diffusion node and amplifier-transistor gate and concomitant parasitic capacitance.

公开(公告)号：US12069875B2

公开(公告)日：2024-08-20

申请号：US17779761

申请日：2020-11-25

Applicant: Sony Semiconductor Solutions Corporation

Inventor： Masashi Nakata

IPC: H10K39/32 ,  H01L27/146 ,  H04N23/13 ,  H04N23/55 ,  H04N23/56 ,  H04N23/57 ,  H04N23/62 ,  H04N25/13 ,  H04N25/131 ,  H04N25/79 ,  H10K30/20

CPC classification number: H10K39/32 ,  H01L27/14621 ,  H01L27/14645 ,  H04N23/13 ,  H04N23/55 ,  H04N23/56 ,  H04N23/57 ,  H04N23/62 ,  H04N25/135 ,  H04N25/79 ,  H10K30/20 ,  H01L27/14625 ,  H01L27/14665 ,  H04N25/131

Abstract: Electronic apparatuses that prevent image quality deterioration of an image captured by a camera while reducing a bezel width are disclosed. In one example, an electronic app mprises a display including a display surface, a first image sensor configured to detect light in a direction incident upon the display surface and arranged under the display surface in a cross sectional view, and a second image sensor disposed separately from the first image sensor, the second image sensor being configured to detect light in the direction incident upon the display surface and arranged at a level lower than the display surface in the cross sectional view. The sensitivity of the first image sensor to a first wavelength band that includes blue light is higher than sensitivity of the second image sensor to the first wavelength band.