公开(公告)号：US11850685B2

公开(公告)日：2023-12-26

申请号：US16290401

申请日：2019-03-01

申请人： FUJI ELECTRIC CO., LTD.

发明人： Hirohiko Watanabe ,  Shunsuke Saito ,  Yoshihiro Kodaira

IPC分类号： B23K35/02 ,  C22C13/02 ,  B23K35/26 ,  B23K1/20 ,  B23K1/00 ,  H01L23/00 ,  H01L21/48 ,  H05K3/34 ,  B23K101/42 ,  B23K35/362

CPC分类号： B23K35/0222 ,  B23K1/0016 ,  B23K1/203 ,  B23K35/025 ,  B23K35/0244 ,  B23K35/26 ,  B23K35/262 ,  C22C13/02 ,  H01L21/4853 ,  H01L24/00 ,  H01L24/29 ,  H01L24/48 ,  B23K35/362 ,  B23K2101/42 ,  H01L24/32 ,  H01L24/45 ,  H01L24/73 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/29111 ,  H01L2224/29211 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/12041 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3511 ,  H05K3/3463 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/29111 ,  H01L2924/01051 ,  H01L2224/29111 ,  H01L2924/01047 ,  H01L2224/29111 ,  H01L2924/01028 ,  H01L2224/29111 ,  H01L2924/01032 ,  H01L2224/29111 ,  H01L2924/01015 ,  H01L2224/05655 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/83455 ,  H01L2924/00014 ,  H01L2224/83447 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2924/00012

摘要： A solder material having a good thermal-cycle fatigue property and wettability. The solder material contains not less than 5.0% by mass and not more than 8.0% by mass Sb, not less than 3.0% by mass and not more than 5.0% by mass Ag, and the balance of Sn and incidental impurities. Also, a semiconductor device may include a joining layer between a semiconductor element and a substrate electrode or a lead frame, the joining layer being obtained by melting this solder material.

公开(公告)号：US11735505B2

公开(公告)日：2023-08-22

申请号：US17316157

申请日：2021-05-10

申请人： Kabushiki Kaisha Toshiba ,  Toshiba Electronic Devices & Storage Corporation

发明人： Hidetoshi Kuraya ,  Satoshi Hattori ,  Kyo Tanabiki

IPC分类号： H01L23/49 ,  H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L23/29

CPC分类号： H01L23/495 ,  H01L21/4842 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/49 ,  H01L24/744 ,  H01L24/77 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/49513 ,  H01L24/32 ,  H01L2224/29101 ,  H01L2224/29118 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/73263 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/84138 ,  H01L2224/84345 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2224/92246 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/37147 ,  H01L2924/00014 ,  H01L2224/29118 ,  H01L2924/01047 ,  H01L2224/29118 ,  H01L2924/0105

摘要： According to one embodiment, a semiconductor device includes a semiconductor chip, first and second conductive members, a first connection member, and a resin portion. The first conductive member includes first and second portions. The second portion is electrically connected to the semiconductor chip. A direction from the semiconductor chip toward the second portion is aligned with a first direction. A direction from the second portion toward the first portion is aligned with a second direction crossing the first direction. The second conductive member includes a third portion. The first connection member is provided between the first and third portion. The first connection member is conductive. The resin portion includes a first partial region. The first partial region is provided around the first and third portions, and the first connection member. The first portion has a first surface opposing the first connection member and including a recess and a protrusion.

公开(公告)号：US20180315697A1

公开(公告)日：2018-11-01

申请号：US16028985

申请日：2018-07-06

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Thomas J. Brunschwiler ,  Sebastian Gerke ,  Stefano Sergio Oggioni

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/04 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/04 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/05147 ,  H01L2224/16227 ,  H01L2924/05442 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/19102

摘要： A circuitized substrate for mounting at least one electronic component having a plurality of terminals. The circuitized substrate includes a first portion of electrical insulating material embedding a first electric circuit for coupling a first subset of the terminals. The first electric circuit including one or more patterned conductive layers of electrically conductive material extending parallel to a plane of the circuitized substrate. The circuitized substrate further includes a second portion of electrically conductive material. One or more insulating elements of electrical insulating material cross the second portion transversally to the plane to insulate a plurality of conductive elements thereof for coupling a second subset of the terminals. One or more auxiliary components of the electronic component are mounted on the second portion. Each auxiliary component having a first terminal and a second terminal coupled with a first one and a second one, respectively, of a pair of the conductive elements.

公开(公告)号：US10079161B2

公开(公告)日：2018-09-18

申请号：US15884979

申请日：2018-01-31

申请人： J-Devices Corporation

发明人： Toshiyuki Inaoka ,  Yuichiro Yoshikawa ,  Atsuhiro Uratsuji ,  Katsushi Yoshimitsu

IPC分类号： H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/367

CPC分类号： H01L21/4871 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15153 ,  H01L2924/15747

摘要： An object of the present invention is to provide a semiconductor package with which it is possible to reduce a volume of an encapsulation resin and to easily embed a resin regardless of thicknesses of semiconductor chips and a small distance between adjacent semiconductor chips, as well as to provide a thin semiconductor package with which a final product includes no support flat plate. To realize this, a semiconductor package having a structure wherein semiconductor chips are accommodated in cavity parts of a support which is formed by copper plating and includes the cavity parts is provided.

公开(公告)号：US20180240743A1

公开(公告)日：2018-08-23

申请号：US15439752

申请日：2017-02-22

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chih Cheng LEE ,  Yuan-Chang SU

IPC分类号： H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683

CPC分类号： H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/00012

摘要： A substrate includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is embedded in the first dielectric structure, and does not protrude from a first surface of the first dielectric structure. The second dielectric structure is disposed on the first surface of the first dielectric structure. The second circuit layer is embedded in the second dielectric structure, and is electrically connected to the first circuit layer. A first surface of the second circuit layer is substantially coplanar with a first surface of the second dielectric structure, and a surface roughness value of a first surface of the first circuit layer is different from a surface roughness value of the first surface of the second circuit layer.

公开(公告)号：US20180211909A1

公开(公告)日：2018-07-26

申请号：US15926287

申请日：2018-03-20

申请人： Samsung Electronics Co., Ltd.

发明人： Soojae PARK ,  Kyujin Lee

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2224/73265 ,  H01L2224/85423 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05432 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/00012

摘要： A package substrate including an insulating layer having a top surface and a bottom surface opposite to the top surface, at least one first copper pattern disposed in the insulating layer and adjacent to the top surface of the insulating layer, at least one second copper pattern disposed on the bottom surface of the insulating layer, and at least one embedded aluminum pad disposed on the at least one first copper pattern, the at least one embedded aluminum pad disposed in the insulating layer such that a top surface of the at least one embedded aluminum pad is exposed by the insulating layer may be provided.

公开(公告)号：US09991181B2

公开(公告)日：2018-06-05

申请号：US15409885

申请日：2017-01-19

申请人： Qorvo US, Inc.

发明人： Walid M. Meliane ,  Kevin J. Anderson ,  Tarak A. Railkar

IPC分类号： H01L23/34 ,  H01L23/10 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/04 ,  H01L21/50 ,  H01L23/66

CPC分类号： H01L23/10 ,  H01L21/50 ,  H01L21/565 ,  H01L23/04 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/6616 ,  H01L2224/16113 ,  H01L2224/16168 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19102 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00014 ,  H01L2924/00012

摘要： The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component, a top electronic component, and an external electronic component. The perimeter wall extends from a periphery of a lower side of the top substrate to a periphery of an upper side of the bottom substrate to form a cavity. The bottom electronic component is mounted on the upper side of the bottom substrate and exposed to the cavity. The top electronic component is mounted on the lower side of the top substrate and exposed to the cavity. And the external electronic component is mounted on an upper side of the top substrate, which is opposite the lower side of the top substrate and not exposed to the cavity.

公开(公告)号：US09960092B2

公开(公告)日：2018-05-01

申请号：US13865318

申请日：2013-04-18

申请人： MITSUBISHI CHEMICAL CORPORATION

发明人： Makoto Ikemoto ,  Yasuhiro Kawase ,  Tomohide Murase ,  Makoto Takahashi ,  Takayoshi Hirai ,  Iho Kamimura

IPC分类号： H01L23/18 ,  H01L23/00 ,  C09D163/00 ,  C08L63/00

CPC分类号： H01L23/18 ,  C08L63/00 ,  C09D163/00 ,  H01L24/13 ,  H01L24/83 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/00

摘要： To provide an interlayer filler composition which, in 3D lamination of semiconductor device chips, forms a highly thermally conductive filling interlayer simultaneously with the bonding of solder bumps or the like and lands between semiconductor device chips, a coating fluid and a process for producing a three-dimensional integrated circuit.An interlayer filler composition for a three-dimensional integrated circuit, which comprises a resin (A) having a melt viscosity at 120° C. of at most 100 Pa·s and a flux (B), the content of the flux (B) being at least 0.1 part by weight and at most 10 parts by weight per 100 parts by weight of the resin (A).

公开(公告)号：US20180096909A1

公开(公告)日：2018-04-05

申请号：US15286428

申请日：2016-10-05

申请人： NXP B.V.

发明人： Wanwisa Peerapaisansap ,  Rungnattha Katworapattra ,  Aricha Olarnwanich

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/29

CPC分类号： H01L23/3135 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/562 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83851 ,  H01L2224/92247 ,  H01L2924/0781 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/0655 ,  H01L2924/00

摘要： A semiconductor device includes a substrate, a semiconductor die mounted on and electrically connected to the substrate, and first and second encapsulants that are different from each other. The first encapsulant covers the die and at least part of the substrate. The second encapsulant covers the first encapsulant and a portion of the substrate that is not covered by the first encapsulant.

公开(公告)号：US20180096903A1

公开(公告)日：2018-04-05

申请号：US15832938

申请日：2017-12-06

申请人： Samsung Electronics Co., Ltd.

发明人： Younghoon Sohn ,  Jinsung Kim ,  Yusin Yang ,  Chungsam Jun

IPC分类号： H01L21/66 ,  H01L23/00 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L21/56 ,  H01L21/67 ,  H01L21/683 ,  H01L21/48 ,  H01L21/02

CPC分类号： H01L22/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/67259 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76895 ,  H01L22/20 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/11 ,  H01L2221/68345 ,  H01L2224/02311 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/14131 ,  H01L2224/96 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/152 ,  H01L2924/15747

摘要： A method of fabricating a package includes providing a mold substrate supporting dies in cavities of a fan-out substrate, detecting positions of the dies with respect to the fan-out substrate, and forming interconnection lines. At least one of the interconnection lines includes a first portion extending from the fan-out substrate to a target position on the cavity disposed between the fan-out substrate and one of the dies the one of the dies disposed at a detected position different from the target position, and a second portion extending from the one die to the fan-out substrate.