公开(公告)号：US12113041B2

公开(公告)日：2024-10-08

申请号：US17717756

申请日：2022-04-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Noriko Okunishi ,  Toshiyuki Hata

IPC: H01L23/00 ,  H01L23/495 ,  H01L29/747 ,  H01L29/78 ,  H02K11/33 ,  H02M7/00

CPC classification number: H01L24/40 ,  H01L24/37 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L23/49562 ,  H01L29/747 ,  H01L29/7813 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/4001 ,  H01L2224/4007 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48245 ,  H01L2924/13018 ,  H01L2924/13091 ,  H02K11/33 ,  H02M7/003

Abstract: In order to reduce on-resistance in a semiconductor device to be used for high current applications, the semiconductor device includes a source terminal lead located between a gate terminal lead and a Kelvin terminal lead in plan view and electrically connected with a source terminal via a plurality of wires.

公开(公告)号：US20240120308A1

公开(公告)日：2024-04-11

申请号：US17960871

申请日：2022-10-06

Applicant: Texas Instruments Incorporated

Inventor： Kwang-Soo Kim ,  Makoto Shibuya ,  Woochan Kim ,  Vivek Arora

IPC: H01L23/00 ,  H01L25/16

CPC classification number: H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/73 ,  H01L24/84 ,  H01L25/16 ,  H01L2224/4001 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/4103 ,  H01L2224/41052 ,  H01L2224/41175 ,  H01L2224/48157 ,  H01L2224/73221 ,  H01L2224/84815 ,  H01L2924/1033 ,  H01L2924/1426 ,  H01L2924/19041 ,  H01L2924/30107

Abstract: An electronic device includes a substrate having first and second conductive traces, a semiconductor die having a transistor with a first terminal and a second terminal, and first and second metal clips. The first metal clip has a first end portion coupled to the first terminal of the transistor, and a second end portion coupled to the first conductive trace of the substrate. The second metal clip has a first end portion coupled to the second terminal of the transistor and a second end portion coupled to the second conductive trace of the substrate, and a middle portion of the second metal clip is spaced apart from and at least partially overlying a portion of the first metal clip.

公开(公告)号：US20240105703A1

公开(公告)日：2024-03-28

申请号：US18322795

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyun Lim ,  Kwangjin Lee ,  Hyunjong Moon ,  Inho Choi

IPC: H01L25/18 ,  G06K19/073 ,  G06V40/13 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/18 ,  G06K19/07354 ,  G06V40/1306 ,  G06V40/1329 ,  H01L23/5388 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L25/50 ,  H01L24/16 ,  H01L24/73 ,  H01L24/84 ,  H01L2224/16145 ,  H01L2224/37013 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40101 ,  H01L2224/40106 ,  H01L2224/40157 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/41176 ,  H01L2224/73205 ,  H01L2224/84005 ,  H01L2924/01039 ,  H01L2924/0665

Abstract: A fingerprint sensor package includes: a first substrate including a core insulating layer including a first surface and a second surface and a through-hole, a first bonding pad on the second surface, and an external connection pad between an edge of the second surface and the first bonding pad; a second substrate in the through-hole and including a third surface and a fourth surface, and including first sensing patterns on the third surface, spaced apart in a first direction, and extending in a second direction, second sensing patterns spaced apart from each other in the second direction and extending in the first direction, and a second bonding pad on the fourth surface; a conductive support electrically connecting the first bonding pad and the second bonding pad and supporting the first substrate and the second substrate; a controller chip on the second substrate; and a molding layer on the second surface.

公开(公告)号：US20180138109A1

公开(公告)日：2018-05-17

申请号：US15871414

申请日：2018-01-15

Applicant: Semiconductor Components Industries, LLC

Inventor： Roger M. Arbuthnot ,  Stephen St. Germain

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/492 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/67 ,  H01L24/73 ,  H01L24/83 ,  H01L24/89 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06051 ,  H01L2224/06181 ,  H01L2224/26175 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/33181 ,  H01L2224/37011 ,  H01L2224/37012 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/45015 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/207 ,  H01L2224/37099

Abstract: In one embodiment, methods for making semiconductor devices are disclosed.

公开(公告)号：US20170162403A1

公开(公告)日：2017-06-08

申请号：US15439817

申请日：2017-02-22

Applicant: VISHAY-SILICONIX

Inventor： Kyle TERRILL ,  Frank KUO ,  Sen MAO

IPC: H01L21/48 ,  H01L23/495 ,  H01L21/56

CPC classification number: H01L25/074 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L23/544 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2223/54486 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/41052 ,  H01L2224/411 ,  H01L2224/41105 ,  H01L2224/4118 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49105 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/8391 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2224/8491 ,  H01L2224/9221 ,  H01L2224/92246 ,  H01L2224/92252 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.

公开(公告)号：US09601453B2

公开(公告)日：2017-03-21

申请号：US14104805

申请日：2013-12-12

Applicant: MagnaChip Semiconductor, Ltd.

Inventor： Francois Hebert

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49513 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L29/1095 ,  H01L29/7809 ,  H01L29/781 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/16145 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40475 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/4118 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73221 ,  H01L2224/73253 ,  H01L2224/73263 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output power device formed in the first die; a second die disposed above the first die, the second die comprising a high-side output power device; and a first connection unit disposed between the first die and the second die.

公开(公告)号：US09595503B2

公开(公告)日：2017-03-14

申请号：US14474420

申请日：2014-09-02

Applicant: Frank Kuo ,  Suresh Belani

Inventor： Frank Kuo ,  Suresh Belani

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L24/90 ,  H01L21/4825 ,  H01L21/56 ,  H01L21/78 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/33 ,  H01L24/34 ,  H01L24/36 ,  H01L24/38 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/84 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/83 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2224/37099

Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing time.

Abstract translation: 提供半导体封装及其制造方法。 在该方法中，使用夹子来引导引线框架和至少一个芯片。 夹具具有至少一个第二连接段，至少一个第三连接段和至少一个中间连接段。 第二连接段分别电连接到芯片的第二导电区域和引线框架的第二引脚，并且第三连接段分别电连接到芯片的第三导电区域和引线框架的第三引脚 。 中间连接段连接至少一个第二连接段和至少一个第三连接段，并在随后的过程中被移除。 因此，本发明不需要使用任何金线，其有效地节省了材料成本和处理时间。

公开(公告)号：US09589929B2

公开(公告)日：2017-03-07

申请号：US13830041

申请日：2013-03-14

Applicant: VISHAY-SILICONIX

Inventor： Kyle Terrill ,  Frank Kuo ,  Sen Mao

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/544 ,  H01L23/31

CPC classification number: H01L25/074 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L23/544 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2223/54486 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/41052 ,  H01L2224/411 ,  H01L2224/41105 ,  H01L2224/4118 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49105 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/8391 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2224/8491 ,  H01L2224/9221 ,  H01L2224/92246 ,  H01L2224/92252 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.

Abstract translation: 在一个实施例中，一种方法可以包括将第一管芯的栅极和源极耦合到引线框架。 第一管芯可以包括位于第一管芯的第一表面上的栅极和源极，以及位于第一管芯的与第一表面相对的第二表面上的漏极。 此外，该方法可以包括将第二管芯的源耦合到第一管芯的漏极。 第二管芯可以包括位于第二管芯的第一表面上的栅极和漏极，以及位于第二管芯的与第一表面相对的第二表面上的源极。

公开(公告)号：US09570379B2

公开(公告)日：2017-02-14

申请号：US14546762

申请日：2014-11-18

Applicant: Infineon Technologies Americas Corp.

Inventor： Eung San Cho

IPC: H01L23/28 ,  H01L23/495 ,  H01L23/00 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L23/49562 ,  H01L23/49524 ,  H01L23/49568 ,  H01L24/36 ,  H01L24/40 ,  H01L24/41 ,  H01L29/2003 ,  H01L29/7788 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

Abstract: In one implementation, a power semiconductor package includes a power transistor having a first power electrode and a gate electrode on its bottom surface, and a second power electrode on its top surface. The first power electrode is configured for attachment to a first partially etched conductive carrier segment and the gate electrode is configured for attachment to a second partially etched conductive carrier segment. The power semiconductor package also includes a power electrode heat spreader situated over the second power electrode and configured for attachment to a power electrode conductive carrier segment.

Abstract translation: 在一个实施方式中，功率半导体封装包括在其底表面上具有第一电源电极和栅电极的功率晶体管，以及在其顶表面上的第二电源电极。 第一电源电极被配置为附接到第一部分蚀刻的导电载体段，并且栅电极被配置为附接到第二部分蚀刻的导电载体段。 功率半导体封装还包括位于第二电源电极上并被配置为附接到功率电极导电载体段的功率电极散热器。

公开(公告)号：US09462091B2

公开(公告)日：2016-10-04

申请号：US14931052

申请日：2015-11-03

Applicant: CANON KABUSHIKI KAISHA

Inventor： Yuji Hara ,  Hisashi Ishikawa

IPC: H04L29/06 ,  G06F15/173 ,  H04L12/40

CPC classification number: H04L69/22 ,  G06F15/17375 ,  H01L2224/37599 ,  H01L2224/4103 ,  H01L2924/00014 ,  H04L12/40 ,  H01L2224/37099

Abstract: There is provided an information processing apparatus including a plurality of communication units connected to one another in a ring shape by a bus, each of the plurality of communication units being connected to one of processing units, each of which executes a predetermined process, and transmitting data processed by the one of the processing units to the bus as a packet, the information processing apparatus transferring data between the processing units and processing the data in a predetermined order. Among the plurality of communication units, in at least one communication unit, a packet including a value indicative of suspension of the process is generated when the connected processing unit has suspended a process, and information showing whether or not the generation unit has generated the packet including the value indicative of suspension of the process is stored.