公开(公告)号：US09425132B2

公开(公告)日：2016-08-23

申请号：US14878408

申请日：2015-10-08

申请人： Texas Instruments Incorporated

发明人： Osvaldo Jorge Lopez ,  Jonathan A. Noquil

IPC分类号： H01L23/495 ,  H01L25/16 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

CPC分类号： H01L23/49575 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/27312 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32147 ,  H01L2224/32148 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/8391 ,  H01L2224/84439 ,  H01L2224/84444 ,  H01L2224/84447 ,  H01L2224/84455 ,  H01L2224/84464 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8491 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/92147 ,  H01L2224/92157 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2224/92252 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/14252 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/20752 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2924/07812 ,  H01L2224/83447 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2224/27

摘要： A system has a leadframe with leads and a pad. The pad surface having a portion recessed with a depth and an outline suitable for attaching a semiconductor chip. A first chip is vertically stacked to the opposite pad surface. A clip is vertically stacked on the first chip and tied to a lead. A second chip has a terminal attached to the recessed portion and terminals co-planar with the un-recessed portion. A second chip is attached to the clip.

摘要翻译： 系统具有带引线和焊盘的引线框架。 焊盘表面具有凹陷的部分，其具有适于附接半导体芯片的深度和轮廓。 第一芯片垂直堆叠到相对的焊盘表面。 一个夹子垂直堆放在第一个芯片上并绑在一个引线上。 第二芯片具有附接到凹部的端子和与未凹部共同的端子。 第二个芯片连接到夹子上。

公开(公告)号：US09184121B2

公开(公告)日：2015-11-10

申请号：US14173147

申请日：2014-02-05

申请人： Texas Instruments Incorporated

发明人： Osvaldo Jorge Lopez ,  Johathan A. Noquil

IPC分类号： H01L23/495 ,  H01L25/16 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

CPC分类号： H01L23/49575 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/27312 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32147 ,  H01L2224/32148 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/8391 ,  H01L2224/84439 ,  H01L2224/84444 ,  H01L2224/84447 ,  H01L2224/84455 ,  H01L2224/84464 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8491 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/92147 ,  H01L2224/92157 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2224/92252 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/14252 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/20752 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2924/07812 ,  H01L2224/83447 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2224/27

摘要： A power supply system (200) has a QFN leadframe with leads and a pad (201, switch node terminal); a pad surface having a portion recessed with a depth (270) and an outline suitable for attaching a semiconductor chip. A first FET chip (220) is vertically stacked to the opposite pad surface. A clip (240) is vertically stacked on the first FET chip and tied to a lead (202, grounded output terminal). A second FET chip (210) has its source terminal attached to the recessed portion and its drain (210a, input terminal) and gate (210b) terminals co-planar with the un-recessed portion. A driver-and-controller chip (230) is attached to the clip. Packaging compound (290) encapsulates the parts but leaves a pad surface and the drain and gate terminals of the second FET chip un-encapsulated.

摘要翻译： 电源系统（200）具有带导线和焊盘（201，开关节点端子）的QFN引线框架; 垫表面，其具有凹入深度（270）的部分和适合于附接半导体芯片的轮廓。 第一FET芯片（220）垂直地堆叠到相对的焊盘表面。 夹子（240）垂直堆叠在第一FET芯片上并连接到引线（202，接地输出端子）。 第二FET芯片（210）的源极端子连接到凹部，其漏极（210a，输入端子）和栅极（210b）端子与未凹入部分共面。 驱动器和控制器芯片（230）附接到夹子。 包装化合物（290）封装部件但留下焊盘表面，并且第二FET芯片的漏极和栅极端子未封装。

公开(公告)号：US20170162403A1

公开(公告)日：2017-06-08

申请号：US15439817

申请日：2017-02-22

申请人： VISHAY-SILICONIX

发明人： Kyle TERRILL ,  Frank KUO ,  Sen MAO

IPC分类号： H01L21/48 ,  H01L23/495 ,  H01L21/56

CPC分类号： H01L25/074 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L23/544 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2223/54486 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/41052 ,  H01L2224/411 ,  H01L2224/41105 ,  H01L2224/4118 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49105 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/8391 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2224/8491 ,  H01L2224/9221 ,  H01L2224/92246 ,  H01L2224/92252 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/05599

摘要： In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.

公开(公告)号：US09589929B2

公开(公告)日：2017-03-07

申请号：US13830041

申请日：2013-03-14

申请人： VISHAY-SILICONIX

发明人： Kyle Terrill ,  Frank Kuo ,  Sen Mao

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L23/544 ,  H01L23/31

CPC分类号： H01L25/074 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L23/544 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2223/54486 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/41052 ,  H01L2224/411 ,  H01L2224/41105 ,  H01L2224/4118 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49105 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/8391 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2224/8491 ,  H01L2224/9221 ,  H01L2224/92246 ,  H01L2224/92252 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/05599

摘要： In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.

摘要翻译： 在一个实施例中，一种方法可以包括将第一管芯的栅极和源极耦合到引线框架。 第一管芯可以包括位于第一管芯的第一表面上的栅极和源极，以及位于第一管芯的与第一表面相对的第二表面上的漏极。 此外，该方法可以包括将第二管芯的源耦合到第一管芯的漏极。 第二管芯可以包括位于第二管芯的第一表面上的栅极和漏极，以及位于第二管芯的与第一表面相对的第二表面上的源极。

公开(公告)号：US20140273344A1

公开(公告)日：2014-09-18

申请号：US13830041

申请日：2013-03-14

申请人： VISHAY-SILICONIX

发明人： Kyle TERRILL ,  Frank KUO ,  Sen MAO

IPC分类号： H01L23/00

CPC分类号： H01L25/074 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49844 ,  H01L23/544 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2223/54486 ,  H01L2224/27318 ,  H01L2224/2732 ,  H01L2224/291 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/41052 ,  H01L2224/411 ,  H01L2224/41105 ,  H01L2224/4118 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49105 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/8391 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2224/8491 ,  H01L2224/9221 ,  H01L2224/92246 ,  H01L2224/92252 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/05599

摘要： In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.

摘要翻译： 在一个实施例中，一种方法可以包括将第一管芯的栅极和源极耦合到引线框架。 第一管芯可以包括位于第一管芯的第一表面上的栅极和源极，以及位于第一管芯的与第一表面相对的第二表面上的漏极。 此外，该方法可以包括将第二管芯的源耦合到第一管芯的漏极。 第二管芯可以包括位于第二管芯的第一表面上的栅极和漏极，以及位于第二管芯的与第一表面相对的第二表面上的源极。

公开(公告)号：US20140175628A1

公开(公告)日：2014-06-26

申请号：US13724006

申请日：2012-12-21

申请人： Hua Pan ,  Yueh-Se Ho ,  Jun Lu ,  Ming-Chen Lu ,  Zhiqiang Niu

发明人： Hua Pan ,  Yueh-Se Ho ,  Jun Lu ,  Ming-Chen Lu ,  Zhiqiang Niu

IPC分类号： H01L23/495 ,  H01L23/00

CPC分类号： H01L24/97 ,  H01L23/3107 ,  H01L23/3171 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/03464 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40479 ,  H01L2224/4048 ,  H01L2224/40499 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48482 ,  H01L2224/48499 ,  H01L2224/48647 ,  H01L2224/48847 ,  H01L2224/73215 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8391 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8491 ,  H01L2224/92 ,  H01L2224/92142 ,  H01L2224/92147 ,  H01L2224/92157 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2224/92246 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/386 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/01079 ,  H01L2224/03 ,  H01L21/78 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/2075 ,  H01L2924/20754 ,  H01L2924/00015 ,  H01L2924/00012

摘要： A semiconductor device comprises a first top electrode and a second top electrode at a front surface of the die, at least a Ni plating layer and an Au plating layer overlaying the Ni plating layer are formed on each of the first top electrode and the second top electrode. A copper clip attaches on the Au plating layer of the second top electrode. A gold (Au) stud bump is formed on the Au plating layer of the first top electrode with a copper wire connected on the stud bump. The Au stud bump is thicker than a thickness of the Au plating layer and thinner than a thickness of the copper clip to avoid copper wire NSOP (non-stick on pad) problem due to Ni plating layer diffusion during the solder reflow process in the copper clip attachment.

摘要翻译： 半导体器件包括在管芯的前表面处的第一顶电极和第二顶电极，在第一顶电极和第二顶部的每一个上形成至少Ni镀层和覆盖Ni镀层的Au镀层 电极。 铜夹附着在第二顶电极的Au镀层上。 在第一顶电极的Au镀层上形成金（Au）柱凸块，铜柱连接在凸块上。 Au凸块比Au镀层的厚度厚，比铜夹的厚度薄，以避免在铜回焊过程中镀镍层扩散的铜线NSOP（不粘垫）问题 夹子附件。

公开(公告)号：US20160027722A1

公开(公告)日：2016-01-28

申请号：US14878408

申请日：2015-10-08

申请人： Texas Instruments Incorporated

发明人： Osvaldo Jorge Lopez ,  Jonathan A. Noquil

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/49575 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/27312 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32147 ,  H01L2224/32148 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/8391 ,  H01L2224/84439 ,  H01L2224/84444 ,  H01L2224/84447 ,  H01L2224/84455 ,  H01L2224/84464 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8491 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/92147 ,  H01L2224/92157 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2224/92252 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/14252 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/20752 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2924/07812 ,  H01L2224/83447 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2224/27

摘要： A system has a leadframe with leads and a pad. The pad surface having a portion recessed with a depth and an outline suitable for attaching a semiconductor chip. A first chip is vertically stacked to the opposite pad surface. A clip is vertically stacked on the first chip and tied to a lead. A second chip has a terminal attached to the recessed portion and terminals co-planar with the un-recessed portion. A second chip is attached to the clip.

摘要翻译： 系统具有带引线和焊盘的引线框架。 焊盘表面具有凹陷的部分，其具有适于附接半导体芯片的深度和轮廓。 第一芯片垂直堆叠到相对的焊盘表面。 一个夹子垂直堆放在第一个芯片上并绑在一个引线上。 第二芯片具有附接到凹部的端子和与未凹部共同的端子。 第二个芯片连接到夹子上。

公开(公告)号：US20150221584A1

公开(公告)日：2015-08-06

申请号：US14173147

申请日：2014-02-05

申请人： Texas Instruments Incorporated

发明人： Osvaldo Jorge Lopez ,  Johathan A. Noquil

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L25/16 ,  H01L23/00

CPC分类号： H01L23/49575 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/27312 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32147 ,  H01L2224/32148 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/37013 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/41051 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48111 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73271 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/83801 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/8391 ,  H01L2224/84439 ,  H01L2224/84444 ,  H01L2224/84447 ,  H01L2224/84455 ,  H01L2224/84464 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8491 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2224/92147 ,  H01L2224/92157 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2224/92252 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/14252 ,  H01L2924/1426 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/20752 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07811 ,  H01L2924/07812 ,  H01L2224/83447 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2224/27

摘要： A power supply system (200) has a QFN leadframe with leads and a pad (201, switch node terminal); a pad surface having a portion recessed with a depth (270) and an outline suitable for attaching a semiconductor chip. A first FET chip (220) is vertically stacked to the opposite pad surface. A clip (240) is vertically stacked on the first FET chip and tied to a lead (202, grounded output terminal). A second FET chip (210) has its source terminal attached to the recessed portion and its drain (210a, input terminal) and gate (210b) terminals co-planar with the un-recessed portion. A driver-and-controller chip (230) is attached to the clip. Packaging compound (290) encapsulates the parts but leaves a pad surface and the drain and gate terminals of the second FET chip un-encapsulated.

摘要翻译： 电源系统（200）具有带导线和焊盘（201，开关节点端子）的QFN引线框架; 垫表面，其具有凹入深度（270）的部分和适合于附接半导体芯片的轮廓。 第一FET芯片（220）垂直地堆叠到相对的焊盘表面。 夹子（240）垂直堆叠在第一FET芯片上并连接到引线（202，接地输出端子）。 第二FET芯片（210）的源极端子连接到凹部，其漏极（210a，输入端子）和栅极（210b）端子与未凹入部分共面。 驱动器和控制器芯片（230）附接到夹子。 包装化合物（290）封装部件但留下焊盘表面，并且第二FET芯片的漏极和栅极端子未封装。