公开(公告)号：US20230369284A1

公开(公告)日：2023-11-16

申请号：US17879585

申请日：2022-08-02

Applicant: PAC TECH - PACKAGING TECHNOLOGIES GMBH

Inventor： RICARDO GEELHAAR ,  MATTHIAS FETTKE

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/85 ,  H01L24/48 ,  H01L24/45 ,  H01L23/49866 ,  H01L2224/85214 ,  H01L24/73 ,  H01L24/16 ,  H01L2224/73257 ,  H01L2224/16225 ,  H01L2224/85439 ,  H01L2224/45147 ,  H01L2224/48499 ,  H01L2224/48476 ,  H01L2224/48105 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2224/8584 ,  H01L2924/40102 ,  H01L2924/1579 ,  H01L2924/15788 ,  H01L2924/15738 ,  H01L23/145

Abstract: A method for forming a contact connection between a chip-and a conductor material formed on a non-conductive substrate, the chip being arranged on the substrate or on another conductor material track, a sinter paste consisting of at least 40% silver or copper being applied to respective chip contact surfaces of the chip and the conductor material track, a contact conductor being immersed in the sinter paste on the chip contact surface and in the sinter paste on the conductor material track, and the contact connection being formed by sintering the sinter paste by means of laser energy.

公开(公告)号：US20180269163A1

公开(公告)日：2018-09-20

申请号：US15885837

申请日：2018-02-01

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Morio IWAMIZU

IPC: H01L23/00 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/45

CPC classification number: H01L23/562 ,  H01L21/28568 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/823475 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/06 ,  H01L27/0617 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827 ,  H01L2224/0345 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/03831 ,  H01L2224/03845 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48477 ,  H01L2224/48499 ,  H01L2924/04941 ,  H01L2924/13055 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01013

Abstract: To protect the insulating film so that crack is not produced in the insulating film even when stress is applied to the semiconductor device. A manufacturing method of a semiconductor device is provided, including: forming an insulating film above a semiconductor substrate; forming, in the insulating film, one or more openings that expose the semiconductor substrate; forming a tungsten portion deposited in the openings and above the insulating film; thinning the tungsten portion on condition that the tungsten portion remains in at least part of a region above the insulating film; and forming an upper electrode above the tungsten portion.

公开(公告)号：US09583455B2

公开(公告)日：2017-02-28

申请号：US15092864

申请日：2016-04-07

Applicant: Renesas Electronics Corporation

Inventor： Kenji Oyachi ,  Tamaki Wada ,  Yuichi Morinaga

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/053 ,  H01L23/31 ,  G06K19/077

CPC classification number: H01L24/48 ,  G06K19/07718 ,  G06K19/0772 ,  G06K19/07722 ,  G06K19/07743 ,  G06K19/07745 ,  H01L23/053 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49855 ,  H01L24/05 ,  H01L24/14 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/49 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/1401 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48499 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83101 ,  H01L2224/83862 ,  H01L2224/85045 ,  H01L2224/85048 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01079 ,  H01L2224/4554

Abstract: Reliability of a semiconductor device is improved. A semiconductor device has a base material of insulating material having a through hole, a terminal formed on a lower surface of the base material, and a semiconductor chip mounted on an upper surface of the base material in a face-up manner. The semiconductor device has a conductive member such as a wire, which electrically connects a pad of the semiconductor chip with an exposed surface of the terminal which is exposed from the through hole of the base material, and has a sealing body for sealing the conductive member, inside of the through hole of the base material, and the semiconductor chip. An anchor is provided in a region of the exposed surface of the terminal which is exposed from the through hole of the base material except for a joint portion joined with the conductive member.

Abstract translation: 提高了半导体器件的可靠性。 半导体器件具有绝缘材料的基材，具有通孔，形成在基材的下表面上的端子和以面朝上的方式安装在基材的上表面上的半导体芯片。 半导体器件具有诸如导线的导电构件，其将半导体芯片的焊盘与从基材的通孔暴露的端子的暴露表面电连接，并且具有用于密封导电构件的密封体 在基材的通孔内部和半导体芯片之间。 在除了与导电部件接合的接合部分之外，从基材的通孔露出的端子的暴露表面的区域中设置有锚。

公开(公告)号：US09536855B2

公开(公告)日：2017-01-03

申请号：US14784127

申请日：2014-03-27

Applicant: MITSUBISHI ELECTRIC CORPORATION

Inventor： Koji Yamazaki ,  Takeshi Araki

IPC: H01L23/00 ,  B23K20/00 ,  B23K35/30 ,  C22C5/06 ,  H01L23/495 ,  H01L23/49

CPC classification number: H01L24/49 ,  B23K20/004 ,  B23K35/3006 ,  C22C5/06 ,  H01L23/49 ,  H01L23/49513 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/04026 ,  H01L2224/05568 ,  H01L2224/05639 ,  H01L2224/26175 ,  H01L2224/2733 ,  H01L2224/29111 ,  H01L2224/32225 ,  H01L2224/325 ,  H01L2224/32507 ,  H01L2224/4501 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/4516 ,  H01L2224/48225 ,  H01L2224/48499 ,  H01L2224/48507 ,  H01L2224/49173 ,  H01L2224/83011 ,  H01L2224/83014 ,  H01L2224/8309 ,  H01L2224/8314 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/85801 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10254 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/12 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A semiconductor device includes, an alloy layer sandwiched between a first Ag layer formed on a mounting board or circuit board and a second Ag layer formed on a semiconductor element, wherein the alloy layer contains an intermetallic compound of Ag3Sn formed by Ag components of the first Ag layer and the second Ag layer and Sn, and wherein a plurality of wires containing Ag are arranged extended from an outside-facing periphery of the alloy layer.

Abstract translation: 半导体装置包括：夹在形成于安装基板或电路基板上的第一Ag层与形成在半导体元件上的第二Ag层之间的合金层，其中，所述合金层含有由所述第一Ag的Ag成分形成的Ag 3 Sn的金属间化合物， Ag层和第二Ag层和Sn，并且其中包含Ag的多个布线从合金层的面向外周延伸设置。

公开(公告)号：US20160293564A1

公开(公告)日：2016-10-06

申请号：US15092864

申请日：2016-04-07

Applicant: Renesas Electronics Corporation

Inventor： Kenji OYACHI ,  Tamaki WADA ,  Yuichi MORINAGA

IPC: H01L23/00 ,  G06K19/077 ,  H01L23/31 ,  H01L23/498 ,  H01L23/053

CPC classification number: H01L24/48 ,  G06K19/07718 ,  G06K19/0772 ,  G06K19/07722 ,  G06K19/07743 ,  G06K19/07745 ,  H01L23/053 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49855 ,  H01L24/05 ,  H01L24/14 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/49 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/1401 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48499 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83101 ,  H01L2224/83862 ,  H01L2224/85045 ,  H01L2224/85048 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01079 ,  H01L2224/4554

Abstract: Reliability of a semiconductor device is improved. A semiconductor device has a base material of insulating material having a through hole, a terminal formed on a lower surface of the base material, and a semiconductor chip mounted on an upper surface of the base material in a face-up manner. The semiconductor device has a conductive member such as a wire, which electrically connects a pad of the semiconductor chip with an exposed surface of the terminal which is exposed from the through hole of the base material, and has a sealing body for sealing the conductive member, inside of the through hole of the base material, and the semiconductor chip. An anchor is provided in a region of the exposed surface of the terminal which is exposed from the through hole of the base material except for a joint portion joined with the conductive member.

Abstract translation: 提高了半导体器件的可靠性。 半导体器件具有绝缘材料的基材，具有通孔，形成在基材的下表面上的端子和以面朝上的方式安装在基材的上表面上的半导体芯片。 半导体器件具有诸如导线的导电构件，其将半导体芯片的焊盘与从基材的通孔暴露的端子的暴露表面电连接，并且具有用于密封导电构件的密封体 在基材的通孔内部和半导体芯片之间。 在除了与导电部件接合的接合部分之外，从基材的通孔露出的端子的暴露表面的区域中设置有锚。

公开(公告)号：US09281289B2

公开(公告)日：2016-03-08

申请号：US14329833

申请日：2014-07-11

Applicant: Renesas Electronics Corporation

Inventor： Yosuke Imazeki ,  Soshi Kuroda

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/065 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0612 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48499 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/4945 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83101 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01079 ,  H01L2224/4554

Abstract: To enhance the reliability of a semiconductor device. The semiconductor device includes a wiring substrate having a plurality of bonding fingers (terminal) formed on a chip-mounting surface, a semiconductor chip mounted on the wiring substrate, a plurality of wires having a ball part and a stitch part respectively. The bonding fingers have a first bonding finger to which the stitch part of the first wire is coupled respectively, and the second bonding finger to which a ball part of the second wire is coupled. In addition, in plan view, the second bonding finger is arranged at a position different from the arrangement of a plurality of first bonding fingers, and the width of the second bonding finger is larger than the width of the first bonding finger.

Abstract translation: 提高半导体器件的可靠性。 半导体器件包括：布线基板，具有形成在芯片安装表面上的多个接合指（端子），安装在布线基板上的半导体芯片，分别具有球部和针迹部分的多个线。 接合指具有第一接合手指，第一线的线迹部分分别连接到第一接合手指，第二接合指状物与第二线的球部分相连接。 此外，在平面图中，第二接合手指布置在与多个第一接合指的布置不同的位置处，并且第二接合指的宽度大于第一接合指的宽度。

公开(公告)号：US09147628B2

公开(公告)日：2015-09-29

申请号：US13535052

申请日：2012-06-27

Applicant: Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess

IPC: H01L23/495 ,  H01L21/60 ,  H01L23/31 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/3135 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L24/85 ,  H01L24/96 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05684 ,  H01L2224/211 ,  H01L2224/24011 ,  H01L2224/24137 ,  H01L2224/245 ,  H01L2224/2518 ,  H01L2224/27318 ,  H01L2224/291 ,  H01L2224/29116 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/40095 ,  H01L2224/40105 ,  H01L2224/40227 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45499 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48472 ,  H01L2224/48476 ,  H01L2224/48499 ,  H01L2224/48611 ,  H01L2224/48618 ,  H01L2224/48624 ,  H01L2224/48638 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48684 ,  H01L2224/48711 ,  H01L2224/48718 ,  H01L2224/48724 ,  H01L2224/48738 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48784 ,  H01L2224/48811 ,  H01L2224/48818 ,  H01L2224/48824 ,  H01L2224/48838 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48884 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85815 ,  H01L2224/92136 ,  H01L2224/92137 ,  H01L2224/92247 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/01044 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0498 ,  H01L2924/0496 ,  H01L2924/0474 ,  H01L2924/0475 ,  H01L2924/0478 ,  H01L2924/0476 ,  H01L2924/0454 ,  H01L2924/0455 ,  H01L2924/0458 ,  H01L2924/0456 ,  H01L2924/00012 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01042 ,  H01L2924/01015 ,  H01L2924/0105 ,  H01L2924/0509 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/0103 ,  H01L2924/01078 ,  H01L2924/0665 ,  H01L2924/01082 ,  H01L2924/01049 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/2075 ,  H01L2924/20754 ,  H01L2224/83205

Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a leadframe having a plurality of leads and a die paddle and a semiconductor module attached to the die paddle of the leadframe. The semiconductor module includes a first semiconductor chip disposed in a first encapsulant. The semiconductor module has a plurality of contact pads coupled to the first semiconductor chip. The semiconductor device further includes a plurality of interconnects coupling the plurality of contact pads with the plurality of leads, and a second encapsulant disposed at the semiconductor module and the leadframe.

Abstract translation: 根据本发明的实施例，半导体器件包括具有多个引线和管芯焊盘的引线框架和连接到引线框架的管芯焊盘的半导体模块。 半导体模块包括设置在第一密封剂中的第一半导体芯片。 半导体模块具有耦合到第一半导体芯片的多个接触焊盘。 半导体器件还包括将多个接触焊盘与多个引线耦合的多个互连以及设置在半导体模块和引线框架处的第二密封剂。

公开(公告)号：US08975760B2

公开(公告)日：2015-03-10

申请号：US13561793

申请日：2012-07-30

Applicant: Shori Fujiwara

Inventor： Shori Fujiwara

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L24/97 ,  H01L23/3128 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48499 ,  H01L2224/4911 ,  H01L2224/49112 ,  H01L2224/4917 ,  H01L2224/49426 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/8385 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/06 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/15798 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2924/3862 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/92247 ,  H01L2924/20752 ,  H01L2224/4554

Abstract: A semiconductor device includes a wiring substrate having first and second connection pads on a main surface thereof, a first semiconductor chip having first electrode pads, a second semiconductor chip having second electrode pads each of which has a size smaller than that of each of the first electrode pads, first wires connecting the first electrode pads with the first connection pads, and second wires connecting the second electrode pads with the second connection pads. The second wires have wide width parts at first ends. The first electrode pads are larger than the wide width parts while the second electrode pads are smaller than the wide width parts. The wide width parts are connected the second connection pads and the second wires have second ends connected to the second electrode pads via bump electrodes which are smaller than the second electrode pads.

Abstract translation: 一种半导体器件包括具有在其主表面上的第一和第二连接焊盘的布线基板，具有第一电极焊盘的第一半导体芯片，具有第二电极焊盘的第二半导体芯片，第二电极焊盘的尺寸小于第一电极焊盘的尺寸， 电极焊盘，将第一电极焊盘与第一连接焊盘连接的第一焊丝，以及将第二电极焊盘与第二连接焊盘连接的第二焊丝。 第二根导线在第一端具有宽的宽度部分。 第一电极焊盘大于宽宽部分，而第二电极焊盘小于宽宽度部分。 大宽度部分连接在第二连接焊盘上，第二导线具有通过小于第二电极焊盘的凸起电极连接到第二电极焊盘的第二端。

公开(公告)号：US20140167292A1

公开(公告)日：2014-06-19

申请号：US14105281

申请日：2013-12-13

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiro MASUMURA ,  Hideki SASAKI ,  Toshiharu OKAMOTO

IPC: H01L25/18 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/4848 ,  H01L2224/48499 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15174 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/20751 ,  H01L2924/01079 ,  H01L2224/4554

Abstract: The present invention provides a multichip package in which a first semiconductor chip having an RF analog circuit area and a digital circuit area, and a second semiconductor chip having a digital circuit area are plane-arranged over an organic multilayer wiring board and coupled to each other by bonding wires. In the multichip package, the first semiconductor chip is made thinner than the second semiconductor chip.

Abstract translation: 本发明提供一种多芯片封装，其中具有RF模拟电路区域和数字电路区域的第一半导体芯片以及具有数字电路区域的第二半导体芯片平面排列在有机多层布线板上并彼此耦合 通过接合线。 在多芯片封装中，使第一半导体芯片比第二半导体芯片薄。

公开(公告)号：US20140001615A1

公开(公告)日：2014-01-02

申请号：US13535052

申请日：2012-06-27

Applicant: Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L23/3135 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L24/85 ,  H01L24/96 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05638 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05684 ,  H01L2224/211 ,  H01L2224/24011 ,  H01L2224/24137 ,  H01L2224/245 ,  H01L2224/2518 ,  H01L2224/27318 ,  H01L2224/291 ,  H01L2224/29116 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/40095 ,  H01L2224/40105 ,  H01L2224/40227 ,  H01L2224/40247 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45499 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48472 ,  H01L2224/48476 ,  H01L2224/48499 ,  H01L2224/48611 ,  H01L2224/48618 ,  H01L2224/48624 ,  H01L2224/48638 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48684 ,  H01L2224/48711 ,  H01L2224/48718 ,  H01L2224/48724 ,  H01L2224/48738 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48784 ,  H01L2224/48811 ,  H01L2224/48818 ,  H01L2224/48824 ,  H01L2224/48838 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48884 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/83815 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85815 ,  H01L2224/92136 ,  H01L2224/92137 ,  H01L2224/92247 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/01044 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0498 ,  H01L2924/0496 ,  H01L2924/0474 ,  H01L2924/0475 ,  H01L2924/0478 ,  H01L2924/0476 ,  H01L2924/0454 ,  H01L2924/0455 ,  H01L2924/0458 ,  H01L2924/0456 ,  H01L2924/00012 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01042 ,  H01L2924/01015 ,  H01L2924/0105 ,  H01L2924/0509 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/0103 ,  H01L2924/01078 ,  H01L2924/0665 ,  H01L2924/01082 ,  H01L2924/01049 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/2075 ,  H01L2924/20754 ,  H01L2224/83205

Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a leadframe having a plurality of leads and a die paddle and a semiconductor module attached to the die paddle of the leadframe. The semiconductor module includes a first semiconductor chip disposed in a first encapsulant. The semiconductor module has a plurality of contact pads coupled to the first semiconductor chip. The semiconductor device further includes a plurality of interconnects coupling the plurality of contact pads with the plurality of leads, and a second encapsulant disposed at the semiconductor module and the leadframe.

Abstract translation: 根据本发明的实施例，半导体器件包括具有多个引线和管芯焊盘的引线框架和连接到引线框架的管芯焊盘的半导体模块。 半导体模块包括设置在第一密封剂中的第一半导体芯片。 半导体模块具有耦合到第一半导体芯片的多个接触焊盘。 半导体器件还包括将多个接触焊盘与多个引线耦合的多个互连以及设置在半导体模块和引线框架处的第二密封剂。