公开(公告)号：US11984418B2

公开(公告)日：2024-05-14

申请号：US17884284

申请日：2022-08-09

Applicant: Texas Instruments Incorporated

Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Frank Pavone ,  Patrick Francis Thompson

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02317 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03502 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05618 ,  H01L2224/05647 ,  H01L2224/11424 ,  H01L2224/1145 ,  H01L2224/11848 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13618 ,  H01L2224/13647 ,  H01L2924/0132

Abstract: A method for manufacturing a package includes positioning a copper layer above a die. A zinc layer is positioned on the copper layer. The zinc and copper layers are then heated to produce a brass layer, the brass layer abutting the copper layer. Further, a polymer layer is positioned abutting the brass layer.

公开(公告)号：US20180350761A1

公开(公告)日：2018-12-06

申请号：US16101114

申请日：2018-08-10

Applicant: Infineon Technologies AG

Inventor： Manfred Schneegans ,  Franziska Haering ,  Hans-Joachim Schulze ,  Bernhard Weidgans

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/532 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L24/05 ,  H01L21/76843 ,  H01L21/76858 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L24/03 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7396 ,  H01L29/7397 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03848 ,  H01L2224/03912 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01074

Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor substrate that has a conductive structure, and forming a precursor auxiliary layer stack on a first section of the conductive structure. The precursor auxiliary layer stack has a precursor adhesion layer and a precursor barrier layer between the precursor adhesion layer and the conductive structure. The precursor adhesion layer contains a second metal. The method further includes forming, on the precursor auxiliary layer stack, a metal structure containing a first metal and forming, from portions of the precursor auxiliary layer stack an adhesive layer containing the first and second metals.

公开(公告)号：US09984993B2

公开(公告)日：2018-05-29

申请号：US15294508

申请日：2016-10-14

Applicant: Advanced Semiconductor, Inc.

Inventor： Min-Fong Shu ,  Yi-Hsiu Tseng ,  Kuan-Neng Chen ,  Shu-Chiao Kuo

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/1182 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13618 ,  H01L2224/13623 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13663 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13676 ,  H01L2224/13678 ,  H01L2224/13687 ,  H01L2224/1607 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81096 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2224/81423 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81457 ,  H01L2224/81463 ,  H01L2224/81464 ,  H01L2224/81466 ,  H01L2224/81476 ,  H01L2224/81478 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81898 ,  H01L2224/83104 ,  H01L2224/83193 ,  H01L2224/92125 ,  H01L2924/00015 ,  H01L2924/15311 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2224/8109 ,  H01L2924/00014 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/053

Abstract: A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.

公开(公告)号：US09960130B2

公开(公告)日：2018-05-01

申请号：US14615436

申请日：2015-02-06

Applicant: United Test and Assembly Center Ltd.

Inventor： Rui Huang ,  Chun Hong Wo ,  Antonio Jr. Bambalan DiMaano

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/0519 ,  H01L2224/0529 ,  H01L2224/05393 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05618 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48227 ,  H01L2224/48453 ,  H01L2224/48465 ,  H01L2224/48507 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01029 ,  H01L2924/00

Abstract: Devices and methods for forming a device are disclosed. The device includes a contact region disposed over a last interconnect level of the device. The device includes a final passivation layer having at least an opening which at least partially exposes a top surface of the contact region and a buffer layer disposed at least over a first exposed portion of the top surface of the contact region. When an electrically conductive interconnection couples to the contact region, the buffer layer absorbs a portion of a force exerted to form an interconnection between the electrically conductive interconnection and the contact region.

公开(公告)号：US20170221842A1

公开(公告)日：2017-08-03

申请号：US15420815

申请日：2017-01-31

Applicant: Infineon Technologies AG

Inventor： Roman ROTH ,  Frank HILLE ,  Hans-Joachim SCHULZE

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02181 ,  H01L2224/0219 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03848 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/491 ,  H01L2224/4911 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2224/45099

Abstract: A power semiconductor device, a power semiconductor module and a power semiconductor device processing method are provided. The power semiconductor device includes a first load terminal structure, a second load terminal structure, and a semiconductor structure electrically coupled to each load terminal structure and configured to carry a load current. The first load terminal structure includes a conductive layer in contact with the semiconductor structure, a bonding block configured to be contacted by at least one bond wire and to receive at least a part of the load current from the at least one bond wire and/or the conductive layer, a support block having a hardness greater than the hardness of the conductive layer and the bonding block. The bonding block is mounted on the conductive layer via the support block, and a zone is arranged within the conductive layer and/or the bonding block, the zone exhibiting nitrogen atoms.

公开(公告)号：US20160240503A1

公开(公告)日：2016-08-18

申请号：US14622494

申请日：2015-02-13

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Min-Fong Shu ,  Yi-Hsiu TSENG ,  Kuan-Neng CHEN ,  Shu-Chiao KUO

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3142 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/564 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/1182 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13618 ,  H01L2224/13623 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13663 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13676 ,  H01L2224/13678 ,  H01L2224/13687 ,  H01L2224/1607 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81096 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81418 ,  H01L2224/81423 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81457 ,  H01L2224/81463 ,  H01L2224/81464 ,  H01L2224/81466 ,  H01L2224/81476 ,  H01L2224/81478 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81898 ,  H01L2224/83104 ,  H01L2224/83193 ,  H01L2224/92125 ,  H01L2924/00015 ,  H01L2924/15311 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2224/8109 ,  H01L2924/00014 ,  H01L2924/01076 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/053

Abstract: The present disclosure relates to bonding structures useful in semiconductor packages and methods of manufacturing the same. In an embodiment, the bonding structure comprises a substrate, having a top surface and including at least one bonding pad, wherein each bonding pad is disposed adjacent to the top surface of the substrate and has a sloped surface; and a semiconductor element including at least one pillar, wherein each pillar is bonded to a portion of the sloped surface of a corresponding bonding pad, and a gap is formed between a sidewall of the pillar and the sloped surface of the corresponding bonding pad.

Abstract translation: 本公开涉及可用于半导体封装的结合结构及其制造方法。 在一个实施例中，接合结构包括具有顶表面并且包括至少一个焊盘的衬底，其中每个接合焊盘邻近衬底的顶表面设置并具有倾斜表面; 以及包括至少一个柱的半导体元件，其中每个柱结合到相应焊盘的倾斜表面的一部分，并且在所述柱的侧壁和相应的焊盘的倾斜表面之间形成间隙。

公开(公告)号：US20160064359A1

公开(公告)日：2016-03-03

申请号：US14935105

申请日：2015-11-06

Applicant: SK hynix Inc.

Inventor： Jong Hoon KIM ,  Han Jun BAE

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81203 ,  H01L2224/81898 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/81

Abstract: Stack packages are provided. The stack package includes a first chip configured to include a first chip body having a top surface and a bottom surface, first through electrodes penetrating the first chip body, and an insulation layer disposed on the bottom surface of the first chip body, and first bumps disposed on the top surface of the first chip body, and a second chip configured to include a second chip body having a top surface and a bottom surface, and second bumps disposed on the top surface of the second chip body. The first and second chips are vertically stacked such that the top surface of the second chip body is directly attached to the first insulation layer and the second bumps of the second chip penetrate the first insulation layer of the first chip to pierce the first through electrodes of the first chip.

Abstract translation: 提供堆栈包。 堆叠封装包括第一芯片，其构造成包括具有顶表面和底表面的第一芯片主体，第一穿透电极穿过第一芯片主体的绝缘层，以及设置在第一芯片主体的底表面上的绝缘层， 设置在第一芯片主体的上表面上，第二芯片构造成包括具有顶表面和底表面的第二芯片主体，以及设置在第二芯片主体的顶表面上的第二凸块。 第一芯片和第二芯片被垂直堆叠，使得第二芯片主体的顶表面直接附接到第一绝缘层，并且第二芯片的第二凸块穿透第一芯片的第一绝缘层以刺穿第一芯片主体的第一穿透电极 第一个芯片。

公开(公告)号：US20160027751A1

公开(公告)日：2016-01-28

申请号：US14686775

申请日：2015-04-14

Applicant: Soon-Bum KIM ,  Tae-Eun KIM ,  Eun-Hye PARK

Inventor： Soon-Bum KIM ,  Tae-Eun KIM ,  Eun-Hye PARK

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05609 ,  H01L2224/05613 ,  H01L2224/05618 ,  H01L2224/0562 ,  H01L2224/05623 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05649 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05681 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13123 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13149 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13172 ,  H01L2224/13181 ,  H01L2224/13565 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16503 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/053

Abstract: Provided is a semiconductor device having a high-reliability solder joint. The semiconductor device includes a high-temperature solder formed on a conductive pad. A low-temperature solder having a lower melting point than the high-temperature solder is formed on the high-temperature solder. A barrier layer is formed between the high-temperature solder and the low-temperature solder. An Sn content of the high-temperature solder is higher than that of the low-temperature solder.

Abstract translation: 提供具有高可靠性焊点的半导体器件。 半导体器件包括形成在导电焊盘上的高温焊料。 在高温焊料上形成熔点低于高温焊料的低温焊料。 在高温焊料和低温焊料之间形成阻挡层。 高温焊料的Sn含量高于低温焊料。

公开(公告)号：US09214410B2

公开(公告)日：2015-12-15

申请号：US14245618

申请日：2014-04-04

Applicant: SK hynix Inc.

Inventor： Jong Hoon Kim ,  Han Jun Bae

IPC: H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81203 ,  H01L2224/81898 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2224/81

Abstract: Stack packages are provided. The stack package includes a first chip and a second chip. The first chip includes a first chip body, first through electrodes penetrating the first chip body, and an insulation layer disposed on a bottom surface of the first chip body. The second chip includes a second chip body and bumps disposed on a top surface of the second chip body. The first and second chips are vertically stacked such that the bumps penetrate the insulation layer to pierce the first through electrodes and the top surface of the second chip body directly contacts the insulation layer. Related fabrication methods, electronic systems and memory cards are also provided.

Abstract translation: 提供堆栈包。 堆叠包装包括第一芯片和第二芯片。 第一芯片包括第一芯片体，穿过第一芯片体的第一穿透电极和设置在第一芯片主体的底表面上的绝缘层。 第二芯片包括设置在第二芯片主体的顶表面上的第二芯片体和凸块。 第一和第二芯片垂直堆叠，使得凸块穿透绝缘层以刺穿第一通孔，第二芯片体的顶表面直接接触绝缘层。 还提供了相关的制造方法，电子系统和存储卡。

公开(公告)号：US09165792B2

公开(公告)日：2015-10-20

申请号：US13625893

申请日：2012-09-25

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Anton Mauder

IPC: H01L23/48 ,  H01L21/50 ,  H01L23/31 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L21/50 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2224/03462 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/08145 ,  H01L2224/11462 ,  H01L2224/13009 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27416 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/80203 ,  H01L2224/80801 ,  H01L2224/80893 ,  H01L2224/80894 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

Abstract: An integrated circuit is provided, the integrated circuit including: a carrier including at least one electronic component and at least one contact area disposed on a first side of the carrier, wherein the at least one electronic component is electrically connected to the at least one contact area; an inorganic material layer wafer bonded to the first side of the carrier, wherein the carrier has a first coefficient of thermal expansion, and wherein the inorganic material layer has a second coefficient of thermal expansion, wherein the second coefficient of thermal expansion has a difference of less than 100% compared with the first coefficient of thermal expansion; and at least one contact via formed through the inorganic material layer, wherein the at least one contact via contacts the at least one contact area.

Abstract translation: 提供集成电路，集成电路包括：载体，其包括至少一个电子部件和布置在载体的第一侧上的至少一个接触区域，其中至少一个电子部件电连接到该至少一个触点 区; 与所述载体的第一侧接合的无机材料层晶片，其中所述载体具有第一热膨胀系数，并且其中所述无机材料层具有第二热膨胀系数，其中所述第二热膨胀系数具有 与第一热膨胀系数相比低于100％; 以及通过无机材料层形成的至少一个接触孔，其中所述至少一个接触通孔接触所述至少一个接触区域。