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1.发明授权公开(公告)号：US08269354B2
公开(公告)日：2012-09-18
申请号：US12908777
申请日：2010-10-20
Applicant: Wen-Hung Hu
Inventor： Wen-Hung Hu
IPC: H01L23/48
CPC classification number: H01L23/49811 , H01L23/498 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/05111 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05568 , H01L2224/056 , H01L2224/05605 , H01L2224/05609 , H01L2224/05611 , H01L2224/05613 , H01L2224/05618 , H01L2224/0562 , H01L2224/05623 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05671 , H01L2924/00014 , H01L2924/14 , H01L2924/00
Abstract: A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package.
Abstract translation: 公开了一种半导体封装基板结构及其制造方法。 该结构包括具有形成在其至少一个表面上的多个电连接焊盘的基板; 多个电镀导电柱，每个覆盖相应的一个电连接焊盘和形成在该基板的表面上的绝缘保护层，并且具有用于使电镀的导电柱露出的露出部分。 本发明允许电镀导电柱之间的间隔最小化，产生集中应力和避免底部填充物的溢出，以及制造的封装的整体高度的降低。
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公开(公告)号：US20100265682A1
公开(公告)日：2010-10-21
申请号：US12427133
申请日：2009-04-21
Applicant: Liane Martinez , Neil McLellan , Silqun Leung , Gabriel Wong
Inventor： Liane Martinez , Neil McLellan , Silqun Leung , Gabriel Wong
CPC classification number: H01L23/49816 , H01L23/50 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05164 , H01L2224/05169 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/05611 , H01L2224/0562 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/01019 , H01L2924/01322 , H01L2924/09701 , H01L2924/15311 , H05K1/0231 , H05K1/145 , H05K3/3442 , H05K2201/1053 , H05K2201/10636 , H05K2201/10734 , Y02P70/611 , Y10T29/4913 , H01L2924/00 , H01L2924/013 , H01L2924/00014
Abstract: Various semiconductor chip packages with undermounted passive devices and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a first side of a carrier substrate where the carrier substrate includes a second side opposite the first side. At least one passive device is coupled to the second side of the carrier substrate. The at least one passive device includes at least one first terminal electrically coupled to the semiconductor chip and at least one second terminal adapted to couple to a printed circuit board.
Abstract translation: 公开了具有未被驱动的无源器件的各种半导体芯片封装及其制造方法。 一方面，提供了一种制造方法，其包括将半导体芯片耦合到载体基板的第一侧，其中载体基板包括与第一侧相对的第二侧。 至少一个无源器件耦合到载体衬底的第二侧。 所述至少一个无源器件包括电耦合到半导体芯片的至少一个第一端子和适于耦合到印刷电路板的至少一个第二端子。
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3.发明申请公开(公告)号：US20080272501A1
公开(公告)日：2008-11-06
申请号：US12114517
申请日：2008-05-02
Applicant: Wen-Hung Hu
Inventor： Wen-Hung Hu
CPC classification number: H01L23/49811 , H01L23/498 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/05111 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05568 , H01L2224/056 , H01L2224/05605 , H01L2224/05609 , H01L2224/05611 , H01L2224/05613 , H01L2224/05618 , H01L2224/0562 , H01L2224/05623 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05671 , H01L2924/00014 , H01L2924/14 , H01L2924/00
Abstract: A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package.
Abstract translation: 公开了一种半导体封装基板结构及其制造方法。 该结构包括具有形成在其至少一个表面上的多个电连接焊盘的基板; 多个电镀导电柱，每个覆盖相应的一个电连接焊盘和形成在该基板的表面上的绝缘保护层，并且具有用于使电镀的导电柱露出的露出部分。 本发明允许电镀导电柱之间的间隔最小化，产生集中应力和避免底部填充物的溢出，以及制造的封装的整体高度的降低。
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公开(公告)号：US09607935B2
公开(公告)日：2017-03-28
申请号：US12427133
申请日：2009-04-21
Applicant: Liane Martinez , Neil McLellan , Silqun Leung , Gabriel Wong
Inventor： Liane Martinez , Neil McLellan , Silqun Leung , Gabriel Wong
CPC classification number: H01L23/49816 , H01L23/50 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05164 , H01L2224/05169 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/05611 , H01L2224/0562 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/01019 , H01L2924/01322 , H01L2924/09701 , H01L2924/15311 , H05K1/0231 , H05K1/145 , H05K3/3442 , H05K2201/1053 , H05K2201/10636 , H05K2201/10734 , Y02P70/611 , Y10T29/4913 , H01L2924/00 , H01L2924/013 , H01L2924/00014
Abstract: Various semiconductor chip packages with undermounted passive devices and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a first side of a carrier substrate where the carrier substrate includes a second side opposite the first side. At least one passive device is coupled to the second side of the carrier substrate. The at least one passive device includes at least one first terminal electrically coupled to the semiconductor chip and at least one second terminal adapted to couple to a printed circuit board.
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5.发明授权公开(公告)号：US07847400B2
公开(公告)日：2010-12-07
申请号：US12114517
申请日：2008-05-02
Applicant: Wen-Hung Hu
Inventor： Wen-Hung Hu
IPC: H01L23/48
CPC classification number: H01L23/49811 , H01L23/498 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/05111 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05568 , H01L2224/056 , H01L2224/05605 , H01L2224/05609 , H01L2224/05611 , H01L2224/05613 , H01L2224/05618 , H01L2224/0562 , H01L2224/05623 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05671 , H01L2924/00014 , H01L2924/14 , H01L2924/00
Abstract: A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package.
Abstract translation: 公开了一种半导体封装基板结构及其制造方法。 该结构包括具有形成在其至少一个表面上的多个电连接焊盘的基板; 多个电镀导电柱，每个覆盖相应的一个电连接焊盘和形成在该基板的表面上的绝缘保护层，并且具有用于使电镀的导电柱露出的露出部分。 本发明允许电镀导电柱之间的间隔最小化，产生集中应力和避免底部填充物的溢出，以及制造的封装的整体高度的降低。
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Patent Agency Ranking
公开(公告)号：US20060113674A1
公开(公告)日：2006-06-01
申请号：US11329081
申请日：2006-01-11
Applicant: Hiroshi Toyoda , Mitsuhiro Nakao , Masahiko Hasunuma , Hisashi Kaneko , Atsuko Sakata , Toshiaki Komukai
Inventor： Hiroshi Toyoda , Mitsuhiro Nakao , Masahiko Hasunuma , Hisashi Kaneko , Atsuko Sakata , Toshiaki Komukai
IPC: H01L23/48
CPC classification number: H01L21/76846 , H01L21/76834 , H01L21/76849 , H01L21/76858 , H01L21/76886 , H01L21/76888 , H01L22/32 , H01L23/53233 , H01L23/53238 , H01L23/53295 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/05017 , H01L2224/05082 , H01L2224/05083 , H01L2224/05093 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05546 , H01L2224/05552 , H01L2224/05557 , H01L2224/05558 , H01L2224/05559 , H01L2224/05567 , H01L2224/05605 , H01L2224/05611 , H01L2224/05613 , H01L2224/05616 , H01L2224/0562 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/13099 , H01L2224/13105 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/45105 , H01L2224/45109 , H01L2224/45111 , H01L2224/45113 , H01L2224/45116 , H01L2224/4512 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/48505 , H01L2224/48611 , H01L2224/48616 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48711 , H01L2224/48716 , H01L2224/48724 , H01L2224/48739 , H01L2224/48747 , H01L2224/48799 , H01L2224/48805 , H01L2224/48811 , H01L2224/48813 , H01L2224/48816 , H01L2224/4882 , H01L2224/48824 , H01L2224/48839 , H01L2224/48844 , H01L2224/48847 , H01L2224/85375 , H01L2924/0002 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01083 , H01L2924/01327 , H01L2924/04953 , H01L2924/05042 , H01L2924/10253 , H01L2924/12042 , H01L2924/00014 , H01L2924/04941 , H01L2224/05609 , H01L2924/00 , H01L2224/48744 , H01L2224/48713 , H01L2224/48705 , H01L2224/4872 , H01L2224/48605 , H01L2224/48613 , H01L2224/4862 , H01L2924/00015
Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.
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公开(公告)号：US20020121703A1
公开(公告)日：2002-09-05
申请号：US10084065
申请日：2002-02-28
Applicant: KABUSHI KAISHA TOSHIBA
Inventor： Hiroshi Toyoda , Mitsuhiro Nakao , Masahiko Hasunuma , Hisashi Kaneko , Atsuko Sakata , Toshiaki Komukai
IPC: H01L029/40 , H01L023/52 , H01L023/48
CPC classification number: H01L21/76846 , H01L21/76834 , H01L21/76849 , H01L21/76858 , H01L21/76886 , H01L21/76888 , H01L22/32 , H01L23/53233 , H01L23/53238 , H01L23/53295 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/05017 , H01L2224/05082 , H01L2224/05083 , H01L2224/05093 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05546 , H01L2224/05552 , H01L2224/05557 , H01L2224/05558 , H01L2224/05559 , H01L2224/05567 , H01L2224/05605 , H01L2224/05611 , H01L2224/05613 , H01L2224/05616 , H01L2224/0562 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/13099 , H01L2224/13105 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/1312 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/45105 , H01L2224/45109 , H01L2224/45111 , H01L2224/45113 , H01L2224/45116 , H01L2224/4512 , H01L2224/45124 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/48505 , H01L2224/48611 , H01L2224/48616 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48711 , H01L2224/48716 , H01L2224/48724 , H01L2224/48739 , H01L2224/48747 , H01L2224/48799 , H01L2224/48805 , H01L2224/48811 , H01L2224/48813 , H01L2224/48816 , H01L2224/4882 , H01L2224/48824 , H01L2224/48839 , H01L2224/48844 , H01L2224/48847 , H01L2224/85375 , H01L2924/0002 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01083 , H01L2924/01327 , H01L2924/04953 , H01L2924/05042 , H01L2924/10253 , H01L2924/12042 , H01L2924/00014 , H01L2924/04941 , H01L2224/05609 , H01L2924/00 , H01L2224/48744 , H01L2224/48713 , H01L2224/48705 , H01L2224/4872 , H01L2224/48605 , H01L2224/48613 , H01L2224/4862 , H01L2924/00015
Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.
Abstract translation: 一种半导体器件，其由形成在半导体衬底上的铜布线层构成，该电极层与铜布线层电连接并具有合金，所述焊接电极层含有铜和氧化倾向高于铜的金属 形成为延伸到底表面，并且具有延伸到焊盘电极层的开口的绝缘保护膜。
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公开(公告)号：US09911706B2
公开(公告)日：2018-03-06
申请号：US14789247
申请日：2015-07-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Chang-hyun Cho , Jun-phyo Lee , Yong-hwan Jeong
CPC classification number: H01L24/06 , H01L22/32 , H01L24/05 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05553 , H01L2224/05557 , H01L2224/05576 , H01L2224/05616 , H01L2224/0562 , H01L2224/05644 , H01L2224/05655 , H01L2224/05686 , H01L2224/0603 , H01L2224/06155 , H01L2224/06156 , H01L2224/16225 , H01L2224/48229 , H01L2924/181 , H01L2924/00014 , H01L2924/05042 , H01L2924/05442 , H01L2924/00012
Abstract: A semiconductor device includes a main pad part and a sub pad part formed in a peripheral area of at least one side of the main pad part. The sub pad part is spaced apart from the main pad part. The sub pad part operates in a first state in which the sub pad part is short-circuited with the main pad part or in a second state in which the sub pad part is open from the main pad part.
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9.发明申请公开(公告)号：US20160027751A1
公开(公告)日：2016-01-28
申请号：US14686775
申请日：2015-04-14
Applicant: Soon-Bum KIM , Tae-Eun KIM , Eun-Hye PARK
Inventor： Soon-Bum KIM , Tae-Eun KIM , Eun-Hye PARK
IPC: H01L23/00
CPC classification number: H01L24/13 , H01L24/11 , H01L24/16 , H01L2224/05008 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05567 , H01L2224/05573 , H01L2224/05609 , H01L2224/05613 , H01L2224/05618 , H01L2224/0562 , H01L2224/05623 , H01L2224/05639 , H01L2224/05644 , H01L2224/05649 , H01L2224/05655 , H01L2224/05657 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/05672 , H01L2224/05681 , H01L2224/11003 , H01L2224/1111 , H01L2224/11334 , H01L2224/11849 , H01L2224/13007 , H01L2224/13017 , H01L2224/13021 , H01L2224/13076 , H01L2224/1308 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/13123 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13149 , H01L2224/13157 , H01L2224/13164 , H01L2224/13166 , H01L2224/13169 , H01L2224/13172 , H01L2224/13181 , H01L2224/13565 , H01L2224/13686 , H01L2224/16058 , H01L2224/16503 , H01L2224/81193 , H01L2224/8181 , H01L2924/014 , H01L2924/00014 , H01L2924/053
Abstract: Provided is a semiconductor device having a high-reliability solder joint. The semiconductor device includes a high-temperature solder formed on a conductive pad. A low-temperature solder having a lower melting point than the high-temperature solder is formed on the high-temperature solder. A barrier layer is formed between the high-temperature solder and the low-temperature solder. An Sn content of the high-temperature solder is higher than that of the low-temperature solder.
Abstract translation: 提供具有高可靠性焊点的半导体器件。 半导体器件包括形成在导电焊盘上的高温焊料。 在高温焊料上形成熔点低于高温焊料的低温焊料。 在高温焊料和低温焊料之间形成阻挡层。 高温焊料的Sn含量高于低温焊料。
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10.发明申请MODIFICATION OF PB-FREE SOLDER ALLOY COMPOSITIONS TO IMPROVE INTERLAYER DIELECTRIC DELAMINATION IN SILICON DEVICES AND ELECTROMIGRATION RESISTANCE IN SOLDER JOINTS 审中-公开改进无铅焊料合金组合物，以改善硅装置中的层间介电分层和焊接接头中的电阻率公开(公告)号：US20090197103A1
公开(公告)日：2009-08-06
申请号：US12254768
申请日：2008-10-20
Applicant: Da-Yuan Shih , Donald W. Henderson , Sung K. Kang , Minhua Lu , Jae-Woong Nah , Kamalesh Srivastava
Inventor： Da-Yuan Shih , Donald W. Henderson , Sung K. Kang , Minhua Lu , Jae-Woong Nah , Kamalesh Srivastava
CPC classification number: B23K1/0016 , B23K1/008 , B23K1/203 , B23K2101/42 , C22C13/00 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/94 , H01L2224/0346 , H01L2224/03464 , H01L2224/0381 , H01L2224/0401 , H01L2224/05147 , H01L2224/05155 , H01L2224/05613 , H01L2224/05618 , H01L2224/0562 , H01L2224/05647 , H01L2224/05655 , H01L2224/11003 , H01L2224/1131 , H01L2224/1132 , H01L2224/11334 , H01L2224/13111 , H01L2224/16227 , H01L2224/16503 , H01L2224/81191 , H01L2224/81395 , H01L2224/81411 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81815 , H01L2224/94 , H01L2924/14 , H01L2924/35121 , H01L2924/3656 , H05K3/3463 , Y10T428/31678 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2924/0103 , H01L2924/01083 , H01L2924/01082 , H01L2924/00012 , H01L2224/11 , H01L2924/01051 , H01L2924/00
Abstract: A solder joint comprising a solder capture pad on a substrate having a circuit; and a lead free solder selected from the group comprising Sn—Ag—Cu solder and Sn—Ag solder adhered to the solder capture pad; the solder selected from the group comprising between 0.1 to 2.0% by weight Sb or Bi, and 0.5 to 3.0% Ag. Formation of voids at an interface between the solder and the solder capture pad is suppressed, by including Zn. Interlayer dielectric delamination is suppressed, and electromigration characteristics are greatly improved. Methods for forming solder joints using the solders.
Abstract translation: 一种焊接接头，包括在具有电路的基板上的焊料捕获垫; 以及选自Sn-Ag-Cu焊料和Sn-Ag焊料的焊料的无铅焊料粘附到焊料捕获垫上; 选自包含0.1至2.0重量％的Sb或Bi和0.5至3.0％Ag的组的焊料。 焊料和焊料捕捉垫之间的界面上的空隙形成通过包含Zn而被抑制。 层间电介质分层被抑制，电迁移特性大大提高。 使用焊料形成焊点的方法。
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