公开(公告)号：US20130252421A1

公开(公告)日：2013-09-26

申请号：US13607381

申请日：2012-09-07

Applicant: Atsuko Sakata ,  Kazuyuki Higashi ,  Akiko Nomachi ,  Takeshi Ishizaki

Inventor： Atsuko Sakata ,  Kazuyuki Higashi ,  Akiko Nomachi ,  Takeshi Ishizaki

IPC: H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/6835 ,  H01L21/76898 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68386

Abstract: According to one embodiment, a method of manufacturing a semiconductor device including forming a metal film on aback surface of a glass substrate which supports a semiconductor substrate on a front surface thereof; forming a metal oxide film by oxidizing the whole or at least a portion of the metal film from the front surface; forming protective film, such as silicon nitride, on the metal oxide film; holding the front surface of the protective film with an electrostatic chuck; and forming a via for electrical connection in the semiconductor substrate while the front surface of the protective film is in contact with by the electrostatic chuck; then using a laser to delaminate the glass substrate from the semiconductor substrate.

Abstract translation: 根据一个实施例，一种制造半导体器件的方法，包括在其表面上支撑半导体衬底的玻璃衬底的表面上形成金属膜; 通过从前表面氧化整个或至少一部分金属膜来形成金属氧化物膜; 在金属氧化物膜上形成诸如氮化硅的保护膜; 用静电卡盘保持保护膜的前表面; 并且在保护膜的前表面通过静电卡盘接触的同时，在半导体衬底中形成用于电连接的通孔; 然后使用激光将玻璃衬底从半导体衬底分层。

公开(公告)号：US08482126B2

公开(公告)日：2013-07-09

申请号：US13224929

申请日：2011-09-02

Applicant: Makoto Wada ,  Yuichi Yamazaki ,  Akihiro Kajita ,  Atsuko Sakata

Inventor： Makoto Wada ,  Yuichi Yamazaki ,  Akihiro Kajita ,  Atsuko Sakata

IPC: H01L23/52 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L23/53276 ,  H01L21/28556 ,  H01L21/76805 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76885 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to an embodiment of the present invention, a device includes a substrate, a base body formed on or above the substrate, and a pair of wirings. The base body has a line shape in a plan view and extends along a length direction. The pair of wirings includes first and second catalyst layers formed on both side surfaces of the base body in the length direction of the base body with sandwiching the base body; and first and second graphene layers formed on both side surfaces of the base body in a manner of contacting the first and second catalyst layers, respectively, and extending along the length direction of the base body, the graphene layers includes a plurality of graphenes laminated perpendicularly with respect to both side surfaces of the base body, respectively.

Abstract translation: 根据本发明的实施例，一种装置包括基板，形成在基板上或上方的基体，以及一对布线。 基体在平面图中具有线状并沿长度方向延伸。 一对配线包括在基体的长度方向上形成在基体的两侧面上的第一和第二催化剂层，夹着基体; 以及分别以与基体的长度方向接触的方式形成在基体的两侧面上的第一和第二石墨烯层，所述石墨烯层包括垂直层叠的多个石墨烯层 分别相对于基体的两个侧面。

公开(公告)号：US08226958B2

公开(公告)日：2012-07-24

申请号：US10551263

申请日：2004-03-25

Applicant: Toshihiro Nakashima ,  Takumi Sasaki ,  Kazuhiko Kimachi ,  Shigeki Kuwata ,  Tsukasa Nishihara ,  Atsuko Sakata ,  Masao Ohkuchi ,  Tomoyuki Koshi ,  Toshiyuki Edano

Inventor： Toshihiro Nakashima ,  Takumi Sasaki ,  Kazuhiko Kimachi ,  Shigeki Kuwata ,  Tsukasa Nishihara ,  Atsuko Sakata ,  Masao Ohkuchi ,  Tomoyuki Koshi ,  Toshiyuki Edano

IPC: A61K39/00 ,  A61K39/02 ,  A61K39/085 ,  C07K1/00 ,  C07K14/00 ,  C07K17/00

CPC classification number: A61K38/164 ,  C07K14/31 ,  C07K16/1271

Abstract: A novel prophylactic/remedy for immunopathy is provided which is not neutralized by a neutralizing antibody to Staphylococcal enterotoxin B (SEB), known as one of superantigens, and may effectively act as a superantigen. A modified SEB having a reduced reactivity with a neutralizing antibody to SEB (anti-SEB antibody) and a prophylactic/remedy for immunopathy comprising as an active ingredient said modified SEB. The modified SEB of the present invention may be prepared with the evolutionary molecular engineering technique by introducing amino acid substitution in the amino acid sequence of SEB, especially at an epitope recognition site of the anti-SEB antibody in the amino acid sequence of SEB.

Abstract translation: 提供一种免疫病的新型预防/治疗方法，其不被被称为超抗原之一的葡萄球菌肠毒素B（SEB）的中和抗体中和，并且可以有效地作为超抗原。 与SEB中和抗体（抗SEB抗体）具有降低的反应性的修饰SEB和用于免疫病的预防/治疗方法，其包含所述经修饰的SEB作为活性成分。 本发明的经修饰的SEB可以通过在SEB的氨基酸序列中引入氨基酸取代，特别是在SEB的氨基酸序列中的抗SEB抗体的表位识别位点处进行进化分子工程技术来制备。

公开(公告)号：US20120080661A1

公开(公告)日：2012-04-05

申请号：US13216435

申请日：2011-08-24

Applicant: Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita ,  Atsuko Sakata

Inventor： Tatsuro Saito ,  Makoto Wada ,  Akihiro Kajita ,  Atsuko Sakata

IPC: H01L29/15 ,  H01L21/441

CPC classification number: H01L21/76885 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, a graphene interconnection includes an insulating film, a catalyst film, and a graphene layer. An insulating film includes an interconnection trench. A catalyst film is formed in the interconnection trench and filling at least a portion of the interconnection trench. A graphene layer is formed on the catalyst film in the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to a bottom surface of the interconnection trench.

Abstract translation: 根据一个实施例，石墨烯互连包括绝缘膜，催化剂膜和石墨烯层。 绝缘膜包括互连沟槽。 在互连沟槽中形成催化剂膜并填充互连沟槽的至少一部分。 在互连沟槽中的催化剂膜上形成石墨烯层，并且包括沿垂直于互连沟槽的底表面的方向堆叠的石墨烯片。

公开(公告)号：US20120049370A1

公开(公告)日：2012-03-01

申请号：US13215463

申请日：2011-08-23

Applicant: Makoto Wada ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Masayuki Kitamura ,  Atsuko Sakata ,  Akihiro Kajita ,  Tadashi Sakai ,  Naohsi Sakuma

Inventor： Makoto Wada ,  Yuichi Yamazaki ,  Masayuki Katagiri ,  Masayuki Kitamura ,  Atsuko Sakata ,  Akihiro Kajita ,  Tadashi Sakai ,  Naohsi Sakuma

IPC: H01L23/522 ,  H01L21/768 ,  B82Y99/00

CPC classification number: H01L23/53276 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1089 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, a carbon nanotube interconnection includes a first conductive layer, an insulating film, a catalyst underlying film, a catalyst deactivation film, a catalyst film, and carbon nanotubes. An insulating film is formed on the first conductive layer and including a hole. An catalyst underlying film is formed on the first conductive layer on a bottom surface in the hole and on the insulating film on a side surface in the hole. A catalyst deactivation film is formed on the catalyst underlying film on the side surface in the hole. A catalyst film is formed on the catalyst underlying film on the bottom surface in the hole and the catalyst deactivation film on the side surface in the hole. Carbon nanotubes are formed in the hole, the carbon nanotubes including one end in contact with the catalyst film on the bottom surface in the hole.

Abstract translation: 根据一个实施例，碳纳米管互连包括第一导电层，绝缘膜，底层催化剂，催化剂失活膜，催化剂膜和碳纳米管。 绝缘膜形成在第一导电层上并包括孔。 在孔的底面上的第一导电层和孔的侧面的绝缘膜上形成催化剂底膜。 在孔中的侧表面上的催化剂底层上形成催化剂失活膜。 在孔的底面的催化剂底层和孔的侧面的催化剂失活膜上形成催化剂膜。 在孔中形成碳纳米管，碳纳米管包括与孔中底表面上的催化剂膜接触的一端。

公开(公告)号：US20060113674A1

公开(公告)日：2006-06-01

申请号：US11329081

申请日：2006-01-11

Applicant: Hiroshi Toyoda ,  Mitsuhiro Nakao ,  Masahiko Hasunuma ,  Hisashi Kaneko ,  Atsuko Sakata ,  Toshiaki Komukai

Inventor： Hiroshi Toyoda ,  Mitsuhiro Nakao ,  Masahiko Hasunuma ,  Hisashi Kaneko ,  Atsuko Sakata ,  Toshiaki Komukai

IPC: H01L23/48

CPC classification number: H01L21/76846 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76886 ,  H01L21/76888 ,  H01L22/32 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05093 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05546 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05605 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/0562 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/45105 ,  H01L2224/45109 ,  H01L2224/45111 ,  H01L2224/45113 ,  H01L2224/45116 ,  H01L2224/4512 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48505 ,  H01L2224/48611 ,  H01L2224/48616 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48711 ,  H01L2224/48716 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48799 ,  H01L2224/48805 ,  H01L2224/48811 ,  H01L2224/48813 ,  H01L2224/48816 ,  H01L2224/4882 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/85375 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2224/05609 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2224/48713 ,  H01L2224/48705 ,  H01L2224/4872 ,  H01L2224/48605 ,  H01L2224/48613 ,  H01L2224/4862 ,  H01L2924/00015

Abstract: A semiconductor device, which is comprised of a copper wiring layer which is formed above a semiconductor substrate, a pad electrode layer which conducts electrically to the copper wiring layer and has an alloy, which contains copper and a metal whose oxidation tendency is higher than copper, formed to extend to the bottom surface, and an insulating protective film which has an opening extended to the pad electrode layer, is provided.

公开(公告)号：US20170229301A9

公开(公告)日：2017-08-10

申请号：US13622089

申请日：2012-09-18

Applicant: Masayuki KITAMURA ,  Atsuko SAKATA ,  Makoto WADA ,  Yuichi YAMAZAKI ,  Masayuki KATAGIRI ,  Akihiro KAJITA ,  Tadashi SAKAI ,  Naoshi SAKUMA ,  Ichiro MIZUSHIMA

Inventor： Masayuki KITAMURA ,  Atsuko SAKATA ,  Makoto WADA ,  Yuichi YAMAZAKI ,  Masayuki KATAGIRI ,  Akihiro KAJITA ,  Tadashi SAKAI ,  Naoshi SAKUMA ,  Ichiro MIZUSHIMA

IPC: H01L21/28 ,  B82Y40/00

CPC classification number: H01L21/76846 ,  H01L21/02373 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76861 ,  H01L21/76876 ,  H01L23/53276 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

公开(公告)号：US08922018B2

公开(公告)日：2014-12-30

申请号：US13427268

申请日：2012-03-22

Applicant: Takeshi Ishizaki ,  Atsuko Sakata ,  Junichi Wada ,  Masahiko Hasunuma

Inventor： Takeshi Ishizaki ,  Atsuko Sakata ,  Junichi Wada ,  Masahiko Hasunuma

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/52 ,  H01L21/44 ,  H01L27/10 ,  H01L21/764 ,  H01L27/06 ,  H01L45/00 ,  H01L27/115 ,  H01L27/24

CPC classification number: H01L27/101 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76888 ,  H01L23/53261 ,  H01L23/53266 ,  H01L27/0688 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, a semiconductor device includes an interconnect provided on a first interlayer insulating film covering a semiconductor substrate in which an element is formed, a cap layer provided on the upper surface of the interconnect, and a barrier film provided between the interconnect and a second interlayer insulating film covering the interconnect. The interconnect includes a high-melting-point conductive layer, and the width of the interconnect is smaller than the width of the cap layer. The barrier film includes a compound of a contained element in the high-melting-point conductive layer.

Abstract translation: 根据一个实施例，半导体器件包括设置在覆盖其中形成元件的半导体衬底的第一层间绝缘膜上的互连，设置在互连的上表面上的覆盖层，以及设置在互连和 覆盖互连的第二层间绝缘膜。 互连包括高熔点导电层，并且互连的宽度小于盖层的宽度。 阻挡膜包括在高熔点导电层中含有元素的化合物。

公开(公告)号：US08637380B2

公开(公告)日：2014-01-28

申请号：US13607381

申请日：2012-09-07

Applicant: Atsuko Sakata ,  Kazuyuki Higashi ,  Akiko Nomachi ,  Takeshi Ishizaki

Inventor： Atsuko Sakata ,  Kazuyuki Higashi ,  Akiko Nomachi ,  Takeshi Ishizaki

IPC: H01L21/30 ,  H01L21/44

CPC classification number: H01L21/76877 ,  H01L21/6835 ,  H01L21/76898 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68386

Abstract: According to one embodiment, a method of manufacturing a semiconductor device including forming a metal film on aback surface of a glass substrate which supports a semiconductor substrate on a front surface thereof; forming a metal oxide film by oxidizing the whole or at least a portion of the metal film from the front surface; forming protective film, such as silicon nitride, on the metal oxide film; holding the front surface of the protective film with an electrostatic chuck; and forming a via for electrical connection in the semiconductor substrate while the front surface of the protective film is in contact with by the electrostatic chuck; then using a laser to delaminate the glass substrate from the semiconductor substrate.

Abstract translation: 根据一个实施例，一种制造半导体器件的方法，包括在其表面上支撑半导体衬底的玻璃衬底的表面上形成金属膜; 通过从前表面氧化整个或至少一部分金属膜来形成金属氧化物膜; 在金属氧化物膜上形成诸如氮化硅的保护膜; 用静电卡盘保持保护膜的前表面; 并且在保护膜的前表面通过静电卡盘接触的同时，在半导体衬底中形成用于电连接的通孔; 然后使用激光将玻璃衬底从半导体衬底分层。

公开(公告)号：US20130217226A1

公开(公告)日：2013-08-22

申请号：US13622089

申请日：2012-09-18

Applicant: Masayuki KITAMURA ,  Atsuko SAKATA ,  Makoto WADA ,  Yuichi YAMAZAKI ,  Masayuki KATAGIRI ,  Akihiro KAJITA ,  Tadashi SAKAI ,  Naoshi SAKUMA ,  Ichiro MIZUSHIMA

Inventor： Masayuki KITAMURA ,  Atsuko SAKATA ,  Makoto WADA ,  Yuichi YAMAZAKI ,  Masayuki KATAGIRI ,  Akihiro KAJITA ,  Tadashi SAKAI ,  Naoshi SAKUMA ,  Ichiro MIZUSHIMA

IPC: H01L21/28 ,  B82Y40/00

CPC classification number: H01L21/76846 ,  H01L21/02373 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76861 ,  H01L21/76876 ,  H01L23/53276 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

Abstract translation: 根据一个实施例，公开了一种用于制造半导体器件的方法。 该方法包括在半导体衬底的表面上方形成助催化剂层和催化剂层。 助催化剂层和催化剂层具有fcc结构。 fcc结构形成为使得fcc结构的（111）面平行于半导体衬底的表面定向。 催化剂包括与助催化剂层接触的部分。 该部分具有fcc结构。 通过氧化和还原处理使催化剂层的暴露表面平坦化。 在催化剂层上形成石墨烯层。