公开(公告)号：US08916417B2

公开(公告)日：2014-12-23

申请号：US13601088

申请日：2012-08-31

申请人： Kazuyuki Higashi ,  Yoshiaki Sugizaki

发明人： Kazuyuki Higashi ,  Yoshiaki Sugizaki

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/4763 ,  H01L21/82 ,  H01L23/538 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/66 ,  H01L23/48

CPC分类号： H01L21/82 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L22/14 ,  H01L22/20 ,  H01L23/481 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73257 ,  H01L2224/83005 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： After stacking m wafers in each of which a plurality of semiconductor chips are formed, the m wafers are diced to semiconductor chips to form a first chip stack having m of the semiconductor chips stacked, and, after stacking n wafers, the n wafers are diced to semiconductor chips to form a second chip stack having n of the semiconductor chips stacked. Next, the first chip stack is sorted according to the number of defective semiconductor chips included in the first chip stack, and the second chip stack is sorted according to the number of defective semiconductor chips included in the second chip stack. Furthermore, the first chip stack or the second chip stack after sorting are combined to form a third chip stack.

摘要翻译： 在堆叠形成多个半导体芯片的m个晶片之后，将m个晶片切割成半导体芯片，以形成堆叠有半导体芯片m的第一芯片堆叠，并且在堆叠n个晶片之后，将n个晶片切割 形成半导体芯片堆叠的n个第二芯片堆叠。 接下来，根据包括在第一芯片堆栈中的缺陷半导体芯片的数量对第一芯片堆叠进行分类，并且根据包括在第二芯片堆栈中的缺陷半导体芯片的数量对第二芯片堆栈进行分类。 此外，将排序之后的第一芯片堆叠或第二芯片堆叠组合以形成第三芯片堆叠。

公开(公告)号：US08426908B2

公开(公告)日：2013-04-23

申请号：US12875766

申请日：2010-09-03

申请人： Kazuyuki Higashi

发明人： Kazuyuki Higashi

IPC分类号： H01L29/792

CPC分类号： H01L27/11578 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/78642

摘要： A nonvolatile semiconductor memory device includes a first region having a plurality of electrically rewritable memory cells disposed therein, and a second region adjacent to the first region. The nonvolatile semiconductor memory device includes a plurality of first conductive layers, a semiconductor layer, a charge storage layer, and an insulating columnar layer. The plurality of first conductive layers are stacked in the first region and the second region, and include a stepped portion in the second region, positions of ends of the plurality of first conductive layers being different in the stepped portion. The semiconductor layer is surrounded by the first conductive layers in the first region, includes a first columnar portion extending in a stacking direction. The charge storage layer is formed between the first conductive layers and a side surface of the first columnar portion. The insulating columnar layer is surrounded by the first conductive layers in the stepped portion, and includes a second columnar portion extending in the stacking direction and comprising an insulator.

摘要翻译： 非易失性半导体存储器件包括具有设置在其中的多个电可重写存储单元的第一区域和与第一区域相邻的第二区域。 非易失性半导体存储器件包括多个第一导电层，半导体层，电荷存储层和绝缘柱状层。 多个第一导电层层叠在第一区域和第二区域中，并且在第二区域中包括阶梯部分，多个第一导电层的端部的位置在阶梯部分中不同。 半导体层被第一区域中的第一导电层围绕，包括沿堆叠方向延伸的第一柱状部分。 电荷存储层形成在第一导电层与第一柱状部分的侧面之间。 绝缘柱状层被台阶部分的第一导电层包围，并且包括在层叠方向上延伸并包括绝缘体的第二柱状部分。

公开(公告)号：US08390055B2

公开(公告)日：2013-03-05

申请号：US12882512

申请日：2010-09-15

申请人： Kazuyuki Higashi ,  Tadashi Iguchi

发明人： Kazuyuki Higashi ,  Tadashi Iguchi

IPC分类号： H01L29/78

CPC分类号： H01L27/11582 ,  G11C16/0483

摘要： A memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The semiconductor layer includes a columnar portion that extends in a perpendicular direction to a substrate. The charge storage layer is formed around a side surface of the columnar portion. The plurality of first conductive layers are formed around the side surface of the columnar portion and the charge storage layer. A control circuit comprises a plurality of second conductive layers, an insulating layer, and a plurality of plug layers. The plurality of second conductive layers are formed in the same layers as the plurality of first conductive layers. The insulating layer is formed penetrating the plurality of second conductive layers in the perpendicular direction. The plurality of plug layers are formed penetrating the insulating layer in the perpendicular direction. The insulating layer has a rectangular shaped cross-section with a constricted portion in a horizontal direction to the substrate. The constricted portion is positioned on a long side of the cross-section.

摘要翻译： 存储器串包括半导体层，电荷存储层和多个第一导电层。 半导体层包括沿与基板垂直的方向延伸的柱状部分。 电荷存储层围绕柱状部分的侧表面形成。 多个第一导电层围绕柱状部分和电荷存储层的侧表面形成。 控制电路包括多个第二导电层，绝缘层和多个插塞层。 多个第二导电层形成在与多个第一导电层相同的层中。 绝缘层形成为沿着垂直方向穿过多个第二导电层。 多个插塞层在垂直方向上形成为穿透绝缘层。 绝缘层具有矩形截面，在基板的水平方向上具有缩颈部分。 收缩部分位于横截面的长边上。

公开(公告)号：US20120319296A1

公开(公告)日：2012-12-20

申请号：US13419751

申请日：2012-03-14

申请人： Kazumichi Tsumura ,  Kazuyuki Higashi

发明人： Kazumichi Tsumura ,  Kazuyuki Higashi

IPC分类号： H01L23/48

CPC分类号： H01L23/562 ,  H01L21/76802 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/585 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/0401

摘要： According to one embodiment, a semiconductor chip includes a semiconductor substrate, a via and an insulating layer. The semiconductor substrate has a first major surface and a second major surface on opposite side from the first major surface. The semiconductor substrate is provided with a circuit section including an element and a wiring and a guard ring structure section surrounding the circuit section on the first major surface side. The via is provided in a via hole extending from the first major surface side to the second major surface side of the semiconductor substrate. The insulating layer is provided in a first trench extending from the first major surface side to the second major surface side of the semiconductor substrate.

摘要翻译： 根据一个实施例，半导体芯片包括半导体衬底，通孔和绝缘层。 半导体衬底具有与第一主表面相对的第一主表面和第二主表面。 半导体基板设置有包括元件和布线的电路部分和围绕第一主表面侧的电路部分的保护环结构部分。 通孔设置在从半导体衬底的第一主表面侧延伸到第二主表面侧的通孔中。 绝缘层设置在从半导体衬底的第一主表面侧延伸到第二主表面侧的第一沟槽中。

公开(公告)号：US08169016B2

公开(公告)日：2012-05-01

申请号：US12874869

申请日：2010-09-02

申请人： Kazuyuki Higashi

发明人： Kazuyuki Higashi

IPC分类号： H01L29/76

CPC分类号： H01L29/792 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

摘要： A plurality of conductive layers are stacked in a first region and a second region. A semiconductor layer is surrounded by the conductive layers in the first region, includes a columnar portion extending in a perpendicular direction with respect to a substrate. A charge storage layer is formed between the conductive layers and a side surface of the columnar portion. The conductive layers includes first trenches, second trenches, and third trenches. The first trenches are arranged in the first region so as to have a first pitch in a first direction. The second trenches are arranged in the second region so as to have a second pitch in the first direction. The third trenches are arranged in the second region so as to have a third pitch in the first direction and so as to be sandwiched by the second trenches.

摘要翻译： 多个导电层堆叠在第一区域和第二区域中。 半导体层被第一区域中的导电层围绕，包括相对于衬底在垂直方向上延伸的柱状部分。 在导电层和柱状部分的侧面之间形成电荷存储层。 导电层包括第一沟槽，第二沟槽和第三沟槽。 第一沟槽被布置在第一区域中，以便在第一方向上具有第一间距。 第二沟槽被布置在第二区域中，以在第一方向上具有第二间距。 第三沟槽被布置在第二区域中，以便在第一方向上具有第三间距并且被第二沟槽夹在中间。

公开(公告)号：US20120061743A1

公开(公告)日：2012-03-15

申请号：US13004229

申请日：2011-01-11

申请人： Nobutaka WATANABE ,  Kazuyuki Higashi ,  Gaku Sudo

发明人： Nobutaka WATANABE ,  Kazuyuki Higashi ,  Gaku Sudo

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11575 ,  H01L27/11582

摘要： According to one embodiment, a semiconductor memory device includes a stacked body, a contact, a semiconductor member, a charge storage layer, and a penetration member. The stacked body includes an electrode film stacked alternately with an insulating film. A configuration of an end portion of the stacked body is a stairstep configuration having a step provided every electrode film. The contact is connected to the electrode film from above the end portion. The semiconductor member is provided in a portion of the stacked body other than the end portion to pierce the stacked body in a stacking direction. The charge storage layer is provided between the electrode film and the semiconductor member. The penetration member pierces the end portion in the stacking direction. The penetration member does not include the same kind of material as the charge storage layer.

摘要翻译： 根据一个实施例，半导体存储器件包括层叠体，接触部，半导体部件，电荷存储层和穿透部件。 层叠体包括与绝缘膜交替堆叠的电极膜。 层叠体的端部的结构是具有设置在每个电极膜上的台阶的台阶构造。 触点从端部的上方连接到电极膜。 半导体构件设置在除了端部之外的层叠体的一部分中，以在层叠方向上刺穿层叠体。 电荷存储层设置在电极膜和半导体部件之间。 穿透构件在层叠方向上刺穿端部。 穿透构件不包含与电荷存储层相同的材料。

公开(公告)号：US20110256672A1

公开(公告)日：2011-10-20

申请号：US13172330

申请日：2011-06-29

申请人： Makoto WADA ,  Kazuyuki HIGASHI ,  Naofumi NAKAMURA ,  Tsuneo UENAKA

发明人： Makoto WADA ,  Kazuyuki HIGASHI ,  Naofumi NAKAMURA ,  Tsuneo UENAKA

IPC分类号： H01L21/8239

CPC分类号： H01L23/481 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/5226 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.

摘要翻译： 非易失性半导体存储器件包括存储器串和布线。 存储器串包括半导体层，电荷存储层和多个第一导电层。 多个第一导电层包括形成为阶梯形状的阶梯部分，使得多个第一导电层的端部的位置彼此不同。 布线包括从包括台阶部分的第一导电层的上表面向上延伸的多个第二导电层。 多个第二导电层形成为使得其上端与平行于基板的表面对齐，并且其直径从其上端向下端减小。 多个第二导电层形成为使得其在垂直方向上的长度越大，其上端的直径越大。

公开(公告)号：US07996813B2

公开(公告)日：2011-08-09

申请号：US12654865

申请日：2010-01-07

申请人： Masaaki Hatano ,  Motoya Okazaki ,  Junichi Wada ,  Takeshi Nishioka ,  Hisashi Kaneko ,  Takeshi Fujimaki ,  Kazuyuki Higashi ,  Kenji Yoshida ,  Noriaki Matsunaga

发明人： Masaaki Hatano ,  Motoya Okazaki ,  Junichi Wada ,  Takeshi Nishioka ,  Hisashi Kaneko ,  Takeshi Fujimaki ,  Kazuyuki Higashi ,  Kenji Yoshida ,  Noriaki Matsunaga

IPC分类号： G06F15/04

CPC分类号： G06F17/5068

摘要： A method for generating a pattern includes reading out an interconnect layout and a hole layout, the interconnect layout prescribing interconnect patterns, the hole layout prescribing hole patterns configured to connect to the interconnect patterns; extracting one of the hole patterns to be connected within the same interconnect layer level to one of the interconnect patterns in a pattern processing area; extracting a first processing area including the extracted hole pattern; calculating a first pattern density of the interconnect patterns included in the first processing area; and generating first additional patterns in the first processing area based on the first pattern density.

摘要翻译： 一种用于产生图案的方法包括：读出互连布局和孔布局;布置规定互连图案的布局布局;布置配置为连接到互连图案的孔图案的孔布局; 在图案处理区域中将在相同互连层级中连接的孔图案中的一个提取到所述互连图案之一; 提取包括所提取的孔图案的第一处理区域; 计算包括在第一处理区域中的互连图案的第一图案密度; 以及基于所述第一图案密度在所述第一处理区域中生成第一附加图案。

公开(公告)号：US20100213526A1

公开(公告)日：2010-08-26

申请号：US12615598

申请日：2009-11-10

申请人： Makoto WADA ,  Kazuyuki HIGASHI ,  Naofumi NAKAMURA ,  Tsuneo UENAKA

发明人： Makoto WADA ,  Kazuyuki HIGASHI ,  Naofumi NAKAMURA ,  Tsuneo UENAKA

IPC分类号： H01L29/792 ,  H01L21/8239

CPC分类号： H01L23/481 ,  H01L21/76808 ,  H01L21/76816 ,  H01L23/5226 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.

摘要翻译： 非易失性半导体存储器件包括存储器串和布线。 存储器串包括半导体层，电荷存储层和多个第一导电层。 多个第一导电层包括形成为阶梯形状的阶梯部分，使得多个第一导电层的端部的位置彼此不同。 布线包括从包括台阶部分的第一导电层的上表面向上延伸的多个第二导电层。 多个第二导电层形成为使得其上端与平行于基板的表面对齐，并且其直径从其上端向下端减小。 多个第二导电层形成为使得其在垂直方向上的长度越大，其上端的直径越大。

公开(公告)号：US07737737B2

公开(公告)日：2010-06-15

申请号：US12128106

申请日：2008-05-28

申请人： Kazuyuki Higashi ,  Shinsuke Yonetani

发明人： Kazuyuki Higashi ,  Shinsuke Yonetani

IPC分类号： H03K3/00

CPC分类号： H03K17/0406 ,  H03K17/04123 ,  H03K17/163 ,  H03K17/168

摘要： A drive circuit for driving a voltage-driven-type element including a gate terminal, an emitter terminal and a collector terminal includes a first semiconductor switch including an output terminal disposed between a power source for the drive circuit and the gate terminal, a first resistor disposed between the output terminal and the gate terminal and a capacitive element connected in parallel with the first semiconductor switch. The capacitive element supplies an external electric charge from the power source to a portion between the gate terminal and the emitter terminal after an internal electric charge accumulated in the portion between the gate terminal and the emitter terminal is supplied to a portion between the gate terminal and the collector terminal.

摘要翻译： 用于驱动包括栅极端子，发射极端子和集电极端子的电压驱动型元件的驱动电路包括：第一半导体开关，包括设置在用于驱动电路的电源和栅极端子之间的输出端子;第一电阻器 设置在输出端子和栅极端子之间以及与第一半导体开关并联连接的电容元件。 在将栅极端子和发射极端子之间的部分积蓄的内部电荷供给到栅极端子与发射极端子之间的部分之后，电容元件将电源从外部电荷提供给栅极端子与发射极端子之间的部分， 集电极端子。