公开(公告)号：US12119338B2

公开(公告)日：2024-10-15

申请号：US18447655

申请日：2023-08-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen

IPC分类号： H01L21/44 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/544 ,  H01L23/58 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/562 ,  H01L23/585 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/97 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/85399

摘要： Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

公开(公告)号：US12096549B1

公开(公告)日：2024-09-17

申请号：US17582734

申请日：2022-01-24

申请人： Vicor Corporation

发明人： Patrizio Vinciarelli ,  Patrick R. Lavery ,  Rudolph F. Mutter ,  Jeffery J. Kirk ,  Andrew T. D'Amico

IPC分类号： H05K1/02 ,  H01L23/053 ,  H01L23/057 ,  H01L23/28 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/16 ,  H05K3/18 ,  H05K3/20 ,  H05K3/24 ,  H05K3/38 ,  H01L21/44 ,  H01L23/14

CPC分类号： H05K1/0204 ,  H05K1/111 ,  H05K1/181 ,  H05K1/186 ,  H05K3/0014 ,  H05K3/0026 ,  H05K3/0044 ,  H05K3/0079 ,  H05K3/16 ,  H05K3/18 ,  H05K3/207 ,  H05K3/24 ,  H05K3/381 ,  H01L21/44 ,  H01L23/053 ,  H01L23/057 ,  H01L23/147 ,  H01L23/28 ,  H05K2201/1003 ,  Y10T29/49146

摘要： Electronic modules having complex contact structures may be formed by encapsulating panels containing pluralities of electronic modules delineated by cut lines and having conductive interconnects buried within the panel along the cut lines. Holes defining contact regions along the electronic module sidewall may be cut into the panel along the cut lines to expose the buried interconnects. The panel may be metallized, e.g. by a series or processes including plating, on selected surfaces including in the holes to form the contacts and other metal structures followed by cutting the panel along the cut lines to singulate the individual electronic models. The contacts may be located in a conductive grove providing a castellated module.

公开(公告)号：US12033868B2

公开(公告)日：2024-07-09

申请号：US18343544

申请日：2023-06-28

申请人： Siliconware Precision Industries Co., Ltd.

发明人： Shu-Chi Chang ,  Wei-Ping Wang ,  Hsien-Lung Hsiao ,  Kaun-I Cheng

IPC分类号： H01L21/44 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/485 ,  H01L23/552 ,  H01L27/06 ,  H01L29/78

CPC分类号： H01L21/44 ,  H01L23/3114 ,  H01L23/485 ,  H01L23/552 ,  H01L24/12 ,  H01L27/0623 ,  H01L29/7834 ,  H01L21/561 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2224/97 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2224/81

摘要： An electronic package and a method for fabrication the same are provided. The method includes: disposing an electronic component on a substrate; forming an encapsulant layer on the substrate to encapsulate the electronic component; and forming a shielding layer made of metal on the encapsulant layer. The shielding layer has an extending portion extending to a lateral side of the substrate along a corner of the encapsulant layer, without extending to a lower side of the substrate. Therefore, the present disclosure prevents the shielding layer from coming into contact with conductive pads disposed on the lower side of the substrate and thereby avoids a short circuit from occurrence.

公开(公告)号：US11881411B2

公开(公告)日：2024-01-23

申请号：US17307737

申请日：2021-05-04

申请人： Applied Materials, Inc.

发明人： Kaushal K. Singh ,  Mei-Yee Shek ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC分类号： H01L21/383 ,  C23C14/58 ,  C23C14/48 ,  H01L21/44

CPC分类号： H01L21/383 ,  C23C14/48 ,  C23C14/5806 ,  H01L21/44

摘要： The present disclosure provides methods for performing an annealing process on a metal containing layer in TFT display applications, semiconductor or memory applications. In one example, a method of forming a metal containing layer on a substrate includes supplying an oxygen containing gas mixture on a substrate in a processing chamber, the substrate comprising a metal containing layer disposed on an optically transparent substrate, maintaining the oxygen containing gas mixture in the processing chamber at a process pressure between about 2 bar and about 50 bar, and thermally annealing the metal containing layer in the presence of the oxygen containing gas mixture.

公开(公告)号：US11798932B2

公开(公告)日：2023-10-24

申请号：US17855664

申请日：2022-06-30

申请人： Intel Corporation

发明人： Russell K. Mortensen ,  Robert M. Nickerson ,  Nicholas R. Watts

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/60 ,  H01L23/02 ,  H01L23/28 ,  H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L23/488 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L25/10 ,  H01L25/11 ,  H01L25/18 ,  H01L23/00 ,  H05K1/11 ,  H05K3/40 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L25/18 ,  H01L21/4846 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/43 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/89 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H05K1/113 ,  H05K3/4038 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/08238 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/107 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/143 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1511 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/381 ,  Y10T29/49124 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/48472 ,  H01L2224/48227 ,  H01L2924/00

摘要： An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

公开(公告)号：US11791269B2

公开(公告)日：2023-10-17

申请号：US16931690

申请日：2020-07-17

申请人： Intel Corporation

发明人： Srinivas V. Pietambaram ,  Rahul N. Manepalli

IPC分类号： H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/10 ,  H05K7/00 ,  H05K7/02 ,  H01L21/02 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/52 ,  H01L21/56 ,  H01L21/60 ,  H01L21/84 ,  H01L21/768 ,  H01L23/00 ,  H01L23/02 ,  H01L23/12 ,  H01L23/13 ,  H01L23/14 ,  H01L23/15 ,  H01L23/18 ,  H01L23/29 ,  H01L23/31 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L23/485 ,  H01L23/495 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/5381 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/17 ,  H01L25/0655 ,  H01L23/5383 ,  H01L24/13 ,  H01L2224/131 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1511 ,  H01L2924/1579 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00

摘要： Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.

公开(公告)号：US11729915B1

公开(公告)日：2023-08-15

申请号：US17700657

申请日：2022-03-22

申请人： TactoTek Oy

发明人： Tomi Simula ,  Tapio Rautio

IPC分类号： H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/22 ,  H05K3/28 ,  H05K3/34 ,  H05K3/46 ,  H01L21/00 ,  H01L21/02 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/60 ,  H01L21/66 ,  H01L21/78 ,  H01L21/673 ,  H01L23/00 ,  H01L23/02 ,  H01L23/04 ,  H01L23/28 ,  H01L23/48 ,  H01L23/49 ,  H01L23/52 ,  H01L23/488 ,  H01L23/495 ,  H01L23/498 ,  H01L23/552 ,  H05K1/03 ,  H05K1/11 ,  H05K3/12

CPC分类号： H05K3/284 ,  H05K1/0393 ,  H05K1/111 ,  H05K3/0067 ,  H05K3/1283 ,  H05K2203/1316 ,  H05K2203/1322

摘要： The method for manufacturing a number of electrical nodes, wherein the method includes providing a number of electronic circuits onto a first substrate, such as on a printed circuit board or other electronics substrate, optionally, a low-temperature co-fired ceramic substrate, wherein each one of the electronic circuits includes a circuit pattern and at least one electronics component in connection with the circuit pattern, wherein the electronic circuits are spaced from each other on the first substrate, thereby defining a blank area surrounding each one of the number of electronic circuits, respectively, and providing potting or casting material to embed each one of the number of electronic circuits in the potting or casting material, and, subsequently, hardening, optionally including curing, the potting or casting material to form a filler material layer of the number of electrical nodes.

公开(公告)号：US11574816B2

公开(公告)日：2023-02-07

申请号：US17104869

申请日：2020-11-25

申请人： STMicroelectronics (Tours) SAS

发明人： Michael De Cruz ,  Olivier Ory

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/56

摘要： A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.

公开(公告)号：US11538735B2

公开(公告)日：2022-12-27

申请号：US16529023

申请日：2019-08-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Rong Chun ,  Kuo Lung Pan ,  Pei-Hsuan Lee ,  Chien Ling Hwang ,  Yu-Chia Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC分类号： H01L23/02 ,  H01L21/44 ,  H01L21/48 ,  H01L23/40 ,  H01L23/00

摘要： In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.

公开(公告)号：US11476203B2

公开(公告)日：2022-10-18

申请号：US17216278

申请日：2021-03-29

申请人： Apple Inc.

发明人： Sanjay Dabral ,  Jun Zhai

IPC分类号： H01L23/48 ,  H01L21/44 ,  H01L23/538 ,  H01L23/488 ,  H01L23/00 ,  H01L25/18 ,  H01L21/66 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/498

摘要： Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.