公开(公告)号：US20240347476A1

公开(公告)日：2024-10-17

申请号：US18632203

申请日：2024-04-10

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Howard E. CHEN ,  Robert Francis DARVEAUX

IPC: H01L23/552 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/66 ,  H01L25/00 ,  H01L25/03 ,  H01L25/10 ,  H01L25/16 ,  H01L25/18 ,  H05K1/18

CPC classification number: H01L23/552 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6836 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/49 ,  H01L24/73 ,  H05K1/181 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2224/16141 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49052 ,  H01L2224/73257 ,  H01L2224/97 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/19106 ,  H01L2924/3025 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: A method for implementing a packaged radio-frequency device is disclosed, including providing a packaging substrate configured to receive one or more components, the packaging substrate including a first side and a second side. The method includes implementing a package on the first side of the packaging substrate, the package including a first overmold structure. The method further includes implementing a set of through-mold connections on the second side of the packaging substrate, the set of through-mold connections defining a mounting area on the second side of the packaging substrate. The method also includes mounting a component to the second side of the packaging substrate. The method additionally includes implementing a second overmold structure on the second side, the second overmold structure substantially encapsulating at least a portion of the component and including an underside surface.

公开(公告)号：US12113004B2

公开(公告)日：2024-10-08

申请号：US17674457

申请日：2022-02-17

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chung-Yu Ke ,  Po-Kai Huang ,  Liang-Pin Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49816 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107

Abstract: An electronic package is provided and includes stacking a first packaging module having a circuit structure, an electronic element, a plurality of first conductive elements and a first packaging layer with a second packaging module having a routing structure, a plurality of second conductive elements and a second packaging layer, so that the second packaging layer is formed on the first packaging layer in a manner that the routing structure is overlapped on the circuit structure, where each of the second conductive elements is correspondingly bonded with each of the first conductive elements. Accordingly, the circuit structure and the routing structure are manufactured separately at the same time, so as to shorten the process time and control the stress distribution on the circuit structure and the routing structure separately.

公开(公告)号：US20240284594A1

公开(公告)日：2024-08-22

申请号：US18653496

申请日：2024-05-02

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Han-Sung BAE ,  Wonkyu KWAK ,  Cheolgeun AN

IPC: H05K1/11 ,  G02F1/1345 ,  H01L23/00 ,  H01L23/495 ,  H05K3/30 ,  H05K3/36

CPC classification number: H05K1/118 ,  G02F1/13458 ,  H01L24/06 ,  H05K1/111 ,  H01L23/49572 ,  H01L2224/50 ,  H01L2224/79 ,  H01L2224/86 ,  H01L2225/06579 ,  H01L2225/107 ,  H05K3/303 ,  H05K3/361 ,  H05K2201/05 ,  H05K2201/058 ,  H05K2201/094 ,  H05K2201/09418 ,  H05K2203/04 ,  Y02P70/50

Abstract: Provided is an electronic component including a pad region including a plurality of pads extending along corresponding extension lines and arranged in a first direction, and a signal wire configured to receive a driving signal from the pad region, wherein the plurality of pads include a plurality of first pads arranged continuously and a plurality of second pads arranged continuously, and extension lines of the plurality of first pads substantially converge into a first point and extension lines of the plurality of second pads substantially converge into a second point different from the first point.

公开(公告)号：US20240282713A1

公开(公告)日：2024-08-22

申请号：US18173027

申请日：2023-02-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hsuan Tsai ,  Yu-Lin CHIANG ,  Chin-Chuan Chang ,  Ying-Ching Shih

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/5386 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5381 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/05687 ,  H01L2224/0569 ,  H01L2224/0801 ,  H01L2224/08058 ,  H01L2224/08059 ,  H01L2224/0807 ,  H01L2224/08235 ,  H01L2224/08238 ,  H01L2224/16235 ,  H01L2224/3201 ,  H01L2224/32059 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/81203 ,  H01L2224/83203 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/107 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/186

Abstract: A package structure includes a first redistribution circuit structure, a first semiconductor die, and a second semiconductor die. The first redistribution circuit structure has a first side and a second side opposite to the first side. The first semiconductor die is disposed over the firs side of the first redistribution circuit structure. The second semiconductor die is disposed over the second side of the first redistribution circuit structure and is electrically connected thereto, where the second semiconductor die includes a substrate, an interconnect structure disposed on the substrate, a plurality of conductive terminals disposed on and electrically connected to the interconnect structure, and a dielectric layer disposed on the interconnect structure and laterally covering the plurality of conductive terminals. A material of the dielectric layer included in the second semiconductor die is different from a material of a dielectric layer included in the first redistribution circuit structure.

公开(公告)号：US20240243056A1

公开(公告)日：2024-07-18

申请号：US18155398

申请日：2023-01-17

Applicant: QUALCOMM Incorporated

Inventor： Yangyang Sun ,  Manuel Aldrete ,  Wei Wang

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/49894 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/105 ,  H01L24/16 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094

Abstract: Integrated circuit (IC) packages employing a re-distribution layer (RDL) substrate(s) with photosensitive non-polymer dielectric material layers for increased package rigidity, and related fabrication methods. To reduce or minimize warpage of an IC package employing a RDL substrate, the RDLs of the RDL substrate are photosensitive non-polymer dielectric material layers. The photosensitive non-polymer dielectric material layers can exhibit increased rigidity as a result of being hardened when exposed to light and cured during fabrication of the RDL substrate. The photosensitive non-polymer dielectric material layers can also exhibit increased rigidity as a result of being an inorganic polymer (e.g., SiOx, SiN material) that has a higher material modulus for increased stiffness and/or a lower coefficient of thermal expansion (CTE) for reduced thermal contraction and expansion, as opposed to for example, an organic polymer material (e.g., Polyimide) which has less stiffness and a higher CTE.

公开(公告)号：US20240213134A1

公开(公告)日：2024-06-27

申请号：US18309768

申请日：2023-04-28

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chih-Hsien CHIU ,  Wen-Jung TSAI ,  Wei-Hao LI ,  Chih-Yi LIAO ,  Cheng-Wei HSU ,  Chih-Yuan TSAI ,  Ko-Wei CHANG ,  Guo-Yu WU

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/49816 ,  H01L25/105 ,  H01L25/165 ,  H01L24/16 ,  H01L2225/107

Abstract: An electronic package is provided, in which an electronic element is disposed on a carrier with a circuit layer, and an encapsulation layer encapsulating the electronic element has an opening exposing the circuit layer, where a metal structure can be contact-bonded on a wall surface of the opening, and a conductive element is formed on the metal structure and electrically connected to the circuit layer. Therefore, no gap is formed between the conductive element and the wall surface of the opening, such that the DC resistance of the conductive element can be reduced.

公开(公告)号：US11979987B2

公开(公告)日：2024-05-07

申请号：US18326426

申请日：2023-05-31

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Han-Sung Bae ,  Wonkyu Kwak ,  Cheolgeun An

IPC: H05K1/18 ,  G02F1/1345 ,  H01L23/00 ,  H05K1/11 ,  H01L23/495 ,  H05K3/30 ,  H05K3/36

CPC classification number: H05K1/118 ,  G02F1/13458 ,  H01L24/06 ,  H05K1/111 ,  H01L23/49572 ,  H01L2224/50 ,  H01L2224/79 ,  H01L2224/86 ,  H01L2225/06579 ,  H01L2225/107 ,  H05K3/303 ,  H05K3/361 ,  H05K2201/05 ,  H05K2201/058 ,  H05K2201/094 ,  H05K2201/09418 ,  H05K2203/04 ,  Y02P70/50

Abstract: Provided is an electronic component including a pad region including a plurality of pads extending along corresponding extension lines and arranged in a first direction, and a signal wire configured to receive a driving signal from the pad region, wherein the plurality of pads include a plurality of first pads arranged continuously and a plurality of second pads arranged continuously, and extension lines of the plurality of first pads substantially converge into a first point and extension lines of the plurality of second pads substantially converge into a second point different from the first point.

公开(公告)号：US11869879B2

公开(公告)日：2024-01-09

申请号：US17965530

申请日：2022-10-13

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Do Hyung Kim ,  Jung Soo Park ,  Seung Chul Han

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L21/48 ,  H01L23/544

CPC classification number: H01L25/0657 ,  H01L21/4867 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/538 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/12 ,  H01L24/81 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L23/49816 ,  H01L23/544 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2224/131 ,  H01L2224/13082 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/107 ,  H01L2225/1058 ,  H01L2924/1531 ,  H01L2924/18161 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/83102 ,  H01L2924/00014

Abstract: A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

公开(公告)号：US20230411365A1

公开(公告)日：2023-12-21

申请号：US18462259

申请日：2023-09-06

Applicant: NVIDIA Corp.

Inventor： Shuo Zhang ,  Eric Zhu ,  Minto Zheng ,  Michael Zhai ,  Town Zhang ,  Jie Ma

IPC: H01L25/10 ,  H01L25/16 ,  H01L23/538 ,  H05K1/18

CPC classification number: H01L25/105 ,  H01L25/16 ,  H01L23/5386 ,  H05K1/181 ,  H01L2225/1094 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10704 ,  H01L2225/107 ,  H05K2201/10015

Abstract: Layout techniques for circuits on substrates are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between circuits while simultaneously providing for the rapid provision of transient power demands to the circuits. The layout techniques may also enable improved thermal management for the circuits.

公开(公告)号：US20230395443A1

公开(公告)日：2023-12-07

申请号：US17805566

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chen LAI ,  Ming-Chih YEW ,  Li-Ling LIAO ,  Yu-Sheng LIN ,  Shin-Puu JENG

IPC: H01L23/13 ,  H01L23/00 ,  H01L25/16 ,  H01L25/10 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/16 ,  H01L25/105 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L21/4846 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/1436 ,  H01L2924/1431 ,  H01L2225/1041 ,  H01L2225/107 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/15153

Abstract: A semiconductor package, which may correspond to a high-performance computing package, includes an interposer, a substrate, and an integrated circuit device between the interposer and the substrate. The integrated circuit device, which may correspond to an integrated passive device, is attached to the interposer within a cavity of the interposer. Attaching the integrated circuit device within the cavity of the interposer creates a clearance between the integrated circuit device and the substrate. In this way, a likelihood of the integrated circuit device contacting the substrate during a bending and/or a deformation of the semiconductor package is reduced. By reducing the likelihood of such contact, damage to the integrated circuit device and/or the substrate may be avoided to increase a reliability and/or yield of the semiconductor package.