公开(公告)号：US12132029B2

公开(公告)日：2024-10-29

申请号：US17648161

申请日：2022-01-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Chia Hu ,  Ming-Fa Chen

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/552 ,  H01L25/00 ,  H01L25/03 ,  H01L25/18

CPC分类号： H01L25/0657 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/08 ,  H01L24/19 ,  H01L24/80 ,  H01L24/94 ,  H01L25/03 ,  H01L25/50 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/08145 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/73259 ,  H01L2224/80895 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/3025 ,  H01L2224/94 ,  H01L2224/80

摘要： A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device.

公开(公告)号：US12125798B2

公开(公告)日：2024-10-22

申请号：US17242704

申请日：2021-04-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Jeng-Shien Hsieh ,  Chuei-Tang Wang ,  Chieh-Yen Chen

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2225/06548

摘要： A semiconductor device includes a first plurality of dies on a wafer, a first redistribution structure over the first plurality of dies, and a second plurality of dies on the first redistribution structure opposite the first plurality of dies. The first redistribution structure includes a first plurality of conductive features. Each die of the first plurality of dies are bonded to respective conductive features of the first plurality of conductive features by metal-metal bonds on a bottom side of the first redistribution structure. Each die of the second plurality of dies are bonded to respective conductive features of the first plurality of conductive features in the first redistribution structure by metal-metal bonds on a top side of the first redistribution structure.

公开(公告)号：US12119315B2

公开(公告)日：2024-10-15

申请号：US17650851

申请日：2022-02-13

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Chih-Wei Chang

IPC分类号： H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L24/05 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L2224/03622 ,  H01L2224/05009 ,  H01L2224/05011 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05073 ,  H01L2224/0801 ,  H01L2224/08055 ,  H01L2224/08056 ,  H01L2224/08059 ,  H01L2224/0807 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80895 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06548

摘要： A chip bonding method includes the following operations. A first chip is provided, which includes a first contact pad including a first portion lower than a first surface of a first substrate and a second portion higher than the first surface of the first substrate to form the stepped first contact pad. A second chip is provided, which includes a second contact pad including a third portion lower than a third surface of a second substrate and a fourth portion higher than the third surface of the second substrate to form the stepped second contact pad. The first chip and the second chip are bonded. The first portion of the first chip contacts with the fourth portion of the second chip, and the second portion of the first chip contacts with the third portion of the second chip.

公开(公告)号：US20240339433A1

公开(公告)日：2024-10-10

申请号：US18610268

申请日：2024-03-20

申请人： Micron Technology, Inc.

发明人： Bharat Bhushan ,  Nevil N. Gajera ,  Akshay N. Singh ,  Kunal R. Parekh

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H10B80/00

CPC分类号： H01L25/0652 ,  H01L23/31 ,  H01L23/481 ,  H01L24/08 ,  H01L24/19 ,  H01L24/20 ,  H01L24/80 ,  H01L24/94 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/19 ,  H01L2224/21 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2225/06548

摘要： A semiconductor device with a through dielectric via is disclosed. The semiconductor device assembly can include a semiconductor die and multiple stacks of semiconductor dies coupled with the semiconductor die at different lateral locations. Dielectric material can be disposed at the semiconductor die between the multiple stacks of semiconductor dies. The through dielectric via can extend entirely through the dielectric material to the semiconductor die such that the through dielectric via couples with circuitry at the semiconductor die. In this way, the through dielectric via can provide power to the semiconductor die (e.g., exclusive of the multiple stacks of semiconductor dies).

公开(公告)号：US20240282684A1

公开(公告)日：2024-08-22

申请号：US18641480

申请日：2024-04-22

申请人： RESONAC CORPORATION

发明人： Kazuyuki MITSUKURA ,  Masaya TOBA ,  Yoshinori EJIRI ,  Kazuhiko KURAFUCHI

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/12 ,  H01L23/14 ,  H01L23/32 ,  H01L23/538 ,  H01L25/065 ,  H05K1/09

CPC分类号： H01L23/49822 ,  H01L21/4857 ,  H01L23/12 ,  H01L23/145 ,  H01L23/32 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/0652 ,  H01L2225/06506 ,  H01L2225/06548 ,  H01L2225/06572 ,  H05K1/09

摘要： An organic interposer includes: a first organic insulating layer including a groove; a first metal wire located in the groove; a barrier metal material covering the first metal wire; and a second metal wire located above the first metal wire, wherein the barrier metal material includes: a first barrier metal film interposed between the first metal wire and an inner surface of the groove; and a second barrier metal film located on the first metal wire, and wherein the second metal wire is in contact with both of the first barrier metal film and the second barrier metal film.

公开(公告)号：US12062633B2

公开(公告)日：2024-08-13

申请号：US17551387

申请日：2021-12-15

申请人： Samsung Electronics Co., Ltd.

发明人： Joungphil Lee ,  Yeongseok Kim

IPC分类号： H01L23/00 ,  C08K3/013 ,  C08K5/00 ,  C08L63/00 ,  H01L21/66 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L24/29 ,  C08K3/013 ,  C08K5/0041 ,  C08L63/00 ,  H01L22/30 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/96 ,  H01L25/0652 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/27515 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32059 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33055 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/16251 ,  H01L2924/182

摘要： Provided is a semiconductor package including: at least one semiconductor device on a first substrate; a non-conductive film (NCF) on the at least one semiconductor device and comprising an irreversible thermochromic pigment; and a molding member on the at least one semiconductor device in a lateral direction, wherein a content of the irreversible thermochromic pigment in the NCF is about 0.1 wt % to about 5 wt % with respect to a weight of the NCF.

公开(公告)号：US12057407B2

公开(公告)日：2024-08-06

申请号：US18362599

申请日：2023-07-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Jeng-Shien Hsieh ,  Chuei-Tang Wang ,  Chieh-Yen Chen

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2225/06548

摘要： A semiconductor device includes a first plurality of dies on a wafer, a first redistribution structure over the first plurality of dies, and a second plurality of dies on the first redistribution structure opposite the first plurality of dies. The first redistribution structure includes a first plurality of conductive features. Each die of the first plurality of dies are bonded to respective conductive features of the first plurality of conductive features by metal-metal bonds on a bottom side of the first redistribution structure. Each die of the second plurality of dies are bonded to respective conductive features of the first plurality of conductive features in the first redistribution structure by metal-metal bonds on a top side of the first redistribution structure.

公开(公告)号：US20240250067A1

公开(公告)日：2024-07-25

申请号：US18598250

申请日：2024-03-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Kuo-Chung Yee ,  Tsung-Ding Wang ,  Chien-Hsun Lee

IPC分类号： H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L21/563 ,  H01L21/565 ,  H01L21/76879 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/08137 ,  H01L2224/08146 ,  H01L2224/12105 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/18162

摘要： A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.

公开(公告)号：US12033976B2

公开(公告)日：2024-07-09

申请号：US18164061

申请日：2023-02-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Kuo-Chung Yee

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10 ,  H01L23/36 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L25/0652 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76885 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/94 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/0231 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/82005 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2224/82 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/73204 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2924/00

摘要： An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs.

公开(公告)号：US20240213235A1

公开(公告)日：2024-06-27

申请号：US18089459

申请日：2022-12-27

申请人： Intel Corporation

发明人： Suddhasattwa Nad ,  Srinivas Pietambaram ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/1427 ,  H01L2924/1431

摘要： An apparatus is provided which comprises: an integrated circuit logic device, an integrated circuit power device conductively coupled with a first surface of the integrated circuit logic device, wherein the integrated circuit power device extends laterally beyond a side of the integrated circuit logic device, one or more vias adjacent the side of the integrated circuit logic device extending from contact with the integrated circuit power device to level with a second surface of the integrated circuit logic device opposite the first surface of the integrated circuit logic device, and conductive contacts on the second surface of the integrated circuit logic device. Other embodiments are also disclosed and claimed.