公开(公告)号：US20240363463A1

公开(公告)日：2024-10-31

申请号：US18766996

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/3114 ,  H01L21/486 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/214 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18162 ,  H01L2924/19041

Abstract: A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.

公开(公告)号：US12080615B2

公开(公告)日：2024-09-03

申请号：US18068010

申请日：2022-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L21/56

CPC classification number: H01L23/3114 ,  H01L21/486 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/214 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2224/94 ,  H01L2224/214 ,  H01L2224/94 ,  H01L2224/83 ,  H01L2224/94 ,  H01L2224/19 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2224/83005

Abstract: A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.

公开(公告)号：US20240088077A1

公开(公告)日：2024-03-14

申请号：US18517774

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L24/05 ,  H01L23/481 ,  H01L24/03 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L2224/05009

Abstract: A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.

公开(公告)号：US20240006270A1

公开(公告)日：2024-01-04

申请号：US17856689

申请日：2022-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Yi Kuo ,  Chen-Hua Yu ,  Kuo-Chung Yee ,  Cheng-Chieh Hsieh ,  Chung-Ju Lee ,  Szu-Wei Lu

IPC: H01L23/473 ,  H01L23/31 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L23/473 ,  H01L23/3135 ,  H01L25/18 ,  H01L25/0655 ,  H01L25/50 ,  H01L21/563 ,  H01L24/94

Abstract: In an embodiment, a package includes an interposer; a first integrated circuit device attached to the interposer, wherein the first integrated circuit device includes a die and a heat dissipation structure, the die having an active surface facing the interposer and an inactive surface opposite to the active surface, the heat dissipation structure attached to the inactive surface of the die and including a plurality of channels recessed from a first surface of the heat dissipation structure, the first surface of the heat dissipation structure facing away from the die; and an encapsulant disposed on the interposer and laterally around the die and the heat dissipation structure, wherein a top surface of the encapsulant is coplanar with the top surface of the heat dissipation structure.

公开(公告)号：US20230114652A1

公开(公告)日：2023-04-13

申请号：US18064713

申请日：2022-12-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC: H01L25/065 ,  H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L21/3105 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538

Abstract: A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.

公开(公告)号：US11574886B2

公开(公告)日：2023-02-07

申请号：US17104588

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/31 ,  H01L23/42 ,  H01L23/00 ,  H01L23/373 ,  H01L21/56 ,  H01L23/433

Abstract: The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes a first chip and a second chip attached to a substrate. A thermal conductivity layer is attached to the first chip. A molding compound laterally surrounds the first chip, the second chip, and the thermal conductivity layer. The second chip extends from the substrate to an imaginary horizontally extending line that extends along a horizontally extending surface of the thermal conductivity layer facing away from the substrate. The imaginary horizontally extending line is parallel to the horizontally extending surface.

公开(公告)号：US11482788B2

公开(公告)日：2022-10-25

申请号：US17013300

申请日：2020-09-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Jeng-Shien Hsieh ,  Wei-Heng Lin ,  Kuo-Chung Yee ,  Chen-Hua Yu

IPC: H01L23/22 ,  H01L23/24 ,  H01Q9/06 ,  H01Q1/22 ,  H01Q3/24 ,  H01Q1/36 ,  H01Q1/48

Abstract: An antenna device includes a package, a radiating element, and a director. The package includes a radio frequency (RF) die and a molding compound in contact with a sidewall of the RF die. The radiating element is in the molding compound and electrically coupled to the RF die. The director is in the molding compound, wherein the radiating element is between the director and the RF die, and a top of the radiating element is substantially coplanar with a top of the director.

公开(公告)号：US11462495B2

公开(公告)日：2022-10-04

申请号：US17077618

申请日：2020-10-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee

IPC: H01L23/00 ,  H01L23/48

Abstract: A method includes forming integrated circuits on a front side of a first chip, performing a backside grinding on the first chip to reveal a plurality of through-vias in the first chip, and forming a first bridge structure on a backside of the first chip using a damascene process. The bridge structure has a first bond pad, a second bond pad, and a conductive trace electrically connecting the first bond pad to the second bond pad. The method further includes bonding a second chip and a third chip to the first chip through face-to-back bonding. A third bond pad of the second chip is bonded to the first bond pad of the first chip. A fourth bond pad of the third chip is bonded to the second bond pad of the first chip.

公开(公告)号：US11139223B2

公开(公告)日：2021-10-05

申请号：US16655257

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chun-Hui Yu ,  Jeng-Nan Hung ,  Kuo-Chung Yee

IPC: H01L23/34 ,  H01L23/473 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31 ,  H01L21/50 ,  H01L21/308

Abstract: A semiconductor package includes a semiconductor package, a cap, a seal, and microstructures. The semiconductor package includes at least one semiconductor die. The cap is disposed over an upper surface of the semiconductor package. The seal is located on the semiconductor package and between the cap and the semiconductor package. The cap includes an inflow channel and an outflow channel. The active surface of the at least one semiconductor die faces away from the cap. The cap and an upper surface of the semiconductor package define a circulation recess providing fluidic communication between the inflow channel and the outflow channel. The seal is disposed around the circulation recess. The microstructures are located within the circulation recess, and the microstructures are connected to at least one of the cap and the at least one semiconductor die.

公开(公告)号：US20210202270A1

公开(公告)日：2021-07-01

申请号：US17205146

申请日：2021-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/36 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor package includes a wafer and at least one chip attached on first portions of an upper surface of the wafer. Further, the semiconductor package includes an insulating barrier layer, a thermally conductive layer, and a heat sink. The insulating barrier layer is arranged over the at least one chip attached on first portions of an upper surface of the wafer. The thermally conductive layer is arranged over the insulating barrier layer and at least partially encapsulates the at least one chip. The heat sink is arranged over the thermally conductive layer.