公开(公告)号：US20240290750A1

公开(公告)日：2024-08-29

申请号：US18367506

申请日：2023-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun LEE ,  Hyunggil BAEK ,  Su-Chang LEE ,  Gyunghwan OH

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/13 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/16 ,  H10B80/00

CPC classification number: H01L25/0652 ,  H01L23/13 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/16 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/19041

Abstract: A semiconductor package includes a substrate including a first region having a recess defined therein and a second region spaced apart from the first region. The second region does not include the recess. A three-dimensional (3D) integrated circuit structure is on the first region. The 3D integrated circuit structure includes a first semiconductor chip die and a second semiconductor chip die disposed on the first semiconductor chip die. A plurality of connecting members electrically connecting the first semiconductor chip die to the substrate. A first side of each connecting member of the plurality of connecting members directly contacts the first semiconductor chip die and a second side that is opposite to the first side directly contacts the first region. A memory structure is disposed in the second region and positioned side by side with the 3D integrated circuit structure.

公开(公告)号：US20240266189A1

公开(公告)日：2024-08-08

申请号：US18635567

申请日：2024-04-15

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Jong Sik Paek ,  Doo Hyun Park ,  Seong Min Seo ,  Sung Geun Kang ,  Yong Song ,  Wang Gu Lee ,  Eun Young Lee ,  Seo Yeon Ahn ,  Pil Je Sung

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/00 ,  H01L23/14 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L25/0655 ,  H01L2021/60022 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19105

Abstract: A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer.

公开(公告)号：US12057432B2

公开(公告)日：2024-08-06

申请号：US16933593

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao Tsai ,  Li-Hui Cheng ,  Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L24/96 ,  H01L21/31053 ,  H01L21/311 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/02205 ,  H01L2224/0231 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13026 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/04642 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/0549 ,  H01L2924/07025 ,  H01L2924/10253 ,  H01L2924/1027 ,  H01L2924/1032 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3512 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00

Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

公开(公告)号：US20240258278A1

公开(公告)日：2024-08-01

申请号：US18500089

申请日：2023-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungchul SHIN ,  Won IL LEE ,  Hyuekjae LEE ,  Enbin JO

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L25/18 ,  H10B80/00 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13117 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16227 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/01058 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433

Abstract: A semiconductor package includes a lower semiconductor chip, a first semiconductor chip, a first through-electrode vertically penetrating the first semiconductor substrate, a first upper pad connected to the first through electrode, a first circuit layer disposed on the lower surface of the first semiconductor substrate, and a first lower pad disposed on a lower surface of the first circuit layer. A second semiconductor chip includes a second through-electrode spaced apart from the first through-electrode and vertically penetrating the second semiconductor substrate. A second upper pad is connected to the second through electrode. A second circuit layer is disposed on the lower surface of the second semiconductor substrate, and a second lower pad is connected to the second through-electrode on the lower surface of the second circuit layer through the second circuit layer and is integrally formed with the first upper pad.

公开(公告)号：US12015023B2

公开(公告)日：2024-06-18

申请号：US17355433

申请日：2021-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Hsien-Pin Hu ,  Yushun Lin ,  Heh-Chang Huang ,  Hsing-Kuo Hsia ,  Chih-Chieh Hung ,  Ying-Ching Shih ,  Chin-Fu Kao ,  Wen-Hsin Wei ,  Li-Chung Kuo ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/4803 ,  H01L21/4853 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2224/97 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2224/81

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

公开(公告)号：US20240071934A1

公开(公告)日：2024-02-29

申请号：US17894200

申请日：2022-08-24

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Seok Ling LIM

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/64 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/4846 ,  H01L23/5386 ,  H01L23/642 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1436 ,  H01L2924/3511

Abstract: The present disclosure is directed to semiconductor packages incorporating composite or hybrid bridges that include first and second interconnect bridges positioned on a substrate and a power corridor with a plurality of vertical channels positioned on the substrate between the first and second interconnect bridges, wherein the power corridor integrally joins the first interconnect bridge to the second interconnect bridge.

公开(公告)号：US20240063133A1

公开(公告)日：2024-02-22

申请号：US17891536

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Beomseok Choi ,  Feras Eid ,  Omkar Karhade ,  Shawna Liff

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L24/08 ,  H01L24/80 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5389 ,  H01L25/0657 ,  H01L25/0652 ,  H01L23/3128 ,  H01L21/56 ,  H01L21/4853 ,  H01L2924/1434 ,  H01L2924/1432 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/08225 ,  H01L2224/08145

Abstract: A multichip composite device includes on- and off-die metallization layers, inorganic dielectric material, and stacked hybrid-bonded dies. On-die metallization layers may be thinner than off-die metallization layers. The multichip composite device may include a structural substrate. Off-die metallization layers may be above and below the stacked hybrid-bonded dies. A substrate may couple the multichip composite device to a power supply in a multichip system. Forming a multichip composite device includes hybrid bonding dies and forming inorganic dielectric material.

公开(公告)号：US11894359B2

公开(公告)日：2024-02-06

申请号：US17574485

申请日：2022-01-12

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark T. Bohr ,  Rajesh Kumar ,  Robert L. Sankman ,  Ravindranath V. Mahajan ,  Wesley D. McCullough

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/48 ,  H01L25/00 ,  H01L23/538 ,  H01L23/522 ,  H01L25/16 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5383 ,  H01L24/09 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/50 ,  H01L23/49816 ,  H01L2924/1432

Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

公开(公告)号：US11798906B2

公开(公告)日：2023-10-24

申请号：US17551548

申请日：2021-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-gi Jin ,  Nae-in Lee ,  Jum-yong Park ,  Jin-ho Chun ,  Seong-min Son ,  Ho-Jin Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L23/3157 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0221 ,  H01L2224/02126 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/02335 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05564 ,  H01L2224/11849 ,  H01L2224/13013 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/13101 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13144 ,  H01L2924/00014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

公开(公告)号：US20230326861A1

公开(公告)日：2023-10-12

申请号：US17715872

申请日：2022-04-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hung-Yi LIN ,  Cheng-Yuan KUNG

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/5381 ,  H01L24/08 ,  H01L25/0652 ,  H01L23/5386 ,  H01L23/5385 ,  H01L2224/08265 ,  H01L2924/1434 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/37001 ,  H01L2224/08145 ,  H01L23/481

Abstract: An electronic package is provided. The electronic package includes a first processing component, a second processing component, and a first memory unit. The first memory unit is over the first processing component and the second processing component. The first processing component and the second processing component are configured to access data stored in the first memory unit.