公开(公告)号：US11830831B2

公开(公告)日：2023-11-28

申请号：US16327810

申请日：2016-09-23

申请人： INTEL CORPORATION

发明人： Georgios Dogiamis ,  Sasha Oster ,  Johanna Swan ,  Shawna Liff ,  Adel Elsherbini ,  Telesphor Kamgaing ,  Aleksandar Aleksov

IPC分类号： H01L23/66 ,  H01P3/12

CPC分类号： H01L23/66 ,  H01P3/121 ,  H01L2223/6627

摘要： Integration of a side-radiating waveguide launcher system into a semiconductor package beneficially permits the coupling of a waveguide directly to the semiconductor package. Included are a first conductive member and a second conductive member separated by a dielectric material. Also included is a conductive structure, such as a plurality of vias, that conductively couples the first conductive member and the second conductive member. Together, the first conductive member, the second conductive member, and the conductive structure form an electrically conductive side-radiating waveguide launcher enclosing shaped space within the dielectric material. The shaped space includes a narrow first end and a wide second end. An RF excitation element is disposed proximate the first end and a waveguide may be operably coupled proximate the second end of the shaped space.

公开(公告)号：US11824018B2

公开(公告)日：2023-11-21

申请号：US18089227

申请日：2022-12-27

申请人： Intel Corporation

发明人： Debendra Mallik ,  Ravindranath Mahajan ,  Robert Sankman ,  Shawna Liff ,  Srinivas Pietambaram ,  Bharat Penmecha

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC分类号： H01L23/562 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511

摘要： Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US11749649B2

公开(公告)日：2023-09-05

申请号：US17399185

申请日：2021-08-11

申请人： Intel Corporation

发明人： Adel Elsherbini ,  Johanna Swan ,  Shawna Liff ,  Patrick Morrow ,  Gerald Pasdast ,  Van Le

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/09 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/0912

摘要： Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

公开(公告)号：US11735551B2

公开(公告)日：2023-08-22

申请号：US16363996

申请日：2019-03-25

申请人： Intel Corporation

发明人： Jimin Yao ,  Shawna Liff ,  Xin Yan ,  Numair Ahmed

IPC分类号： H01L23/00

CPC分类号： H01L24/17 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13014 ,  H01L2224/1319 ,  H01L2224/1357 ,  H01L2224/13147 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/171 ,  H01L2224/812 ,  H01L2224/81139 ,  H01L2224/81815 ,  H01L2924/014

摘要： Embodiments herein relate to systems, apparatuses, or processes directed to an interconnect joint that includes multiple core balls within a solder compound where the multiple core balls are substantially linearly aligned. The multiple core balls, which may include copper or be a polymer, couple with each other within the solder and form a substantially linear alignment during reflow. In embodiments, four or more core balls may be used to achieve a high aspect ratio interconnect joint with a tight pitch.

公开(公告)号：US11581238B2

公开(公告)日：2023-02-14

申请号：US17318887

申请日：2021-05-12

申请人： Intel Corporation

发明人： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Jimin Yao ,  Veronica Strong

IPC分类号： H01L23/373 ,  H01L21/768 ,  H01L25/065 ,  H01L23/48

摘要： A heat spreading material is integrated into a composite die structure including a first IC die having a first dielectric material and a first electrical interconnect structure, and a second IC die having a second dielectric material and a second electrical interconnect structure. The composite die structure may include a composite electrical interconnect structure comprising the first interconnect structure in direct contact with the second interconnect structure at a bond interface. The heat spreading material may be within at least a portion of a dielectric area through which the bond interface extends. The heat spreading material may be located within one or more dielectric materials surrounding the composite interconnect structure, and direct a flow of heat generated by one or more of the first and second IC dies.

公开(公告)号：US11569428B2

公开(公告)日：2023-01-31

申请号：US16347097

申请日：2016-12-27

申请人： Intel Corporation

发明人： Jeanette M. Roberts ,  Adel A. Elsherbini ,  Shawna Liff ,  Johanna M. Swan ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Ravi Pillarisetty ,  Hubert C. George ,  James S. Clarke

IPC分类号： H01L27/32 ,  H01L39/04 ,  G06N10/00 ,  H01L39/02 ,  H01L39/22 ,  H01L39/24 ,  H01L25/00 ,  H01L23/48 ,  H01L23/00 ,  H01L27/18 ,  B82Y10/00 ,  H01L23/538 ,  H01L29/66

摘要： One superconducting qubit device package disclosed herein includes a die having a first face and an opposing second face, and a package substrate having a first face and an opposing second face. The die includes a quantum device including a plurality of superconducting qubits and a plurality of resonators on the first face of the die, and a plurality of conductive pathways coupled between conductive contacts at the first face of the die and associated ones of the plurality of superconducting qubits or of the plurality of resonators. The second face of the package substrate also includes conductive contacts. The device package further includes first level interconnects disposed between the first face of the die and the second face of the package substrate, coupling the conductive contacts at the first face of the die with associated conductive contacts at the second face of the package substrate.

公开(公告)号：US20220399249A1

公开(公告)日：2022-12-15

申请号：US17346895

申请日：2021-06-14

申请人： Intel Corporation

发明人： Georgios Dogiamis ,  Qiang Yu ,  Feras Eid ,  Adel Elsherbini ,  Kimin Jun ,  Johanna Swan ,  Shawna Liff

IPC分类号： H01L23/473 ,  H01L23/13 ,  H01L23/538 ,  H05K7/20 ,  H01L25/065

摘要： An integrated circuit (IC) package may be fabricated having an interposer, one or more microfluidic channels through the interposer, a first IC chip attached to a first side of the interposer, and a second IC chip attached to a second side of the interposer, where the first side of the interposer includes first bond pads coupled to first bond pads of the first IC chip, and the second side of the interposer includes second bond pads coupled to first bond pads of the second IC chip. In an embodiment of the present description, a liquid cooled three-dimensional IC (3DIC) package may be formed with the IC package, where at least two IC devices may be stacked with a liquid cooled interposer. In a further embodiment, the liquid cooled 3DIC package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

公开(公告)号：US20220037281A1

公开(公告)日：2022-02-03

申请号：US17500824

申请日：2021-10-13

申请人： Intel Corporation

发明人： Adel Elsherbini ,  Patrick Morrow ,  Johanna Swan ,  Shawna Liff ,  Mauro Kobrinksy ,  Van Le ,  Gerald Pasdast

IPC分类号： H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L25/18 ,  H01L25/00 ,  H01L21/768 ,  H01L21/82 ,  H01L23/48

摘要： A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.

公开(公告)号：US20210202377A1

公开(公告)日：2021-07-01

申请号：US16727747

申请日：2019-12-26

申请人： Intel Corporation

发明人： Adel Elsherbini ,  Mauro Kobrinsky ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast ,  Sathya Narasimman Tiagaraj

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528

摘要： An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

公开(公告)号：US11049791B1

公开(公告)日：2021-06-29

申请号：US16727703

申请日：2019-12-26

申请人： Intel Corporation

发明人： Shawna Liff ,  Adel Elsherbini ,  Johanna Swan ,  Jimin Yao ,  Veronica Strong

IPC分类号： H01L23/373 ,  H01L21/768 ,  H01L25/065 ,  H01L23/48

摘要： A heat spreading material is integrated into a composite die structure including a first IC die having a first dielectric material and a first electrical interconnect structure, and a second IC die having a second dielectric material and a second electrical interconnect structure. The composite die structure may include a composite electrical interconnect structure comprising the first interconnect structure in direct contact with the second interconnect structure at a bond interface. The heat spreading material may be within at least a portion of a dielectric area through which the bond interface extends. The heat spreading material may be located within one or more dielectric materials surrounding the composite interconnect structure, and direct a flow of heat generated by one or more of the first and second IC dies.