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公开(公告)号：US20240363570A1
公开(公告)日：2024-10-31
申请号：US18141456
申请日：2023-04-30
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/16 , H01L23/31 , H01L23/4951 , H01L2224/03614 , H01L2224/03912 , H01L2224/05022 , H01L2224/05124 , H01L2224/05562 , H01L2224/05582 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05672 , H01L2224/0568 , H01L2224/05681 , H01L2224/05684 , H01L2224/11462 , H01L2224/11464 , H01L2224/11831 , H01L2224/13018 , H01L2224/13147 , H01L2224/16245
摘要： A semiconductor package comprises an integrated circuit having a contact and a conductive bump directly attached to the contact. The conductive bump has a sidewall with a roughened surface. A leadframe is electrically coupled to the conductive bump. An integrated circuit package mold covers portions of the conductive bump and the lead frame, the roughened surface of the conductive bump is configured to interlock with the integrated circuit package mold. An electrically conductive adhesive couples the conductive bump to the lead frame. The conductive bump comprises copper in one arrangement. The roughened surface of the conductive bump includes grooves along grain boundaries that separate copper grains. The roughened surface of the conductive bump is formed by etching with a diluted sulfuric peroxide solution.
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公开(公告)号：US20240363549A1
公开(公告)日：2024-10-31
申请号：US18613040
申请日：2024-03-21
申请人： Innolux Corporation
发明人： Wei-Yuan Cheng , Ju-Li Wang
IPC分类号： H01L23/00 , H01L21/48 , H01L23/367 , H01L23/538 , H01L25/16
CPC分类号： H01L23/562 , H01L21/4846 , H01L23/367 , H01L23/5384 , H01L23/5386 , H01L24/32 , H01L24/33 , H01L25/16 , H01L24/13 , H01L24/16 , H01L24/73 , H01L2224/13105 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16227 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/73204
摘要： An electronic device includes a substrate, a circuit layer, at least one electronic unit, a stress adjustment layer, and a buffer layer. The substrate has a first surface and a second surface opposite to each other and at least one side connected to the first surface and the second surface. The circuit layer is disposed on the first surface of the substrate. The at least one electronic unit is electronically connected to the circuit layer. The stress adjustment layer is disposed on the second surface of the substrate. The buffer layer surrounds the substrate, wherein the stress adjustment layer is located between the substrate and the buffer layer, and the buffer layer is in contact with the at least one side of the substrate.
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公开(公告)号：US20240332272A1
公开(公告)日：2024-10-03
申请号：US18190885
申请日：2023-03-27
发明人： Sang Yun MA , Dong Hee KANG
IPC分类号： H01L25/16 , H01L23/13 , H01L23/367 , H01L23/552
CPC分类号： H01L25/165 , H01L23/13 , H01L23/3675 , H01L23/552 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/73 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13184 , H01L2224/16227 , H01L2224/2919 , H01L2224/29191 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2924/0132 , H01L2924/0665 , H01L2924/069 , H01L2924/0695 , H01L2924/07025 , H01L2924/0715
摘要： In one example, an electronic device includes a substrate with a substrate first side; a substrate second side opposite to the substrate first side, a substrate lateral side connecting the substrate first side to the substrate second side, a dielectric structure, and a conductive structure. A substrate dock includes a substrate dock base at the substrate first side and a first substrate dock sidewall extending upward from the substrate dock base. The substrate dock base and the first substrate dock sidewall define a substrate dock cavity. A cover structure includes a cover sidewall with a cover sidewall lower side. An interface material couples the cover sidewall to the substrate dock. An electronic component is coupled to the conductive structure. Other examples and related methods are also disclosed herein.
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公开(公告)号：US20240332208A1
公开(公告)日：2024-10-03
申请号：US18226994
申请日：2023-07-27
发明人： Chi Hyeon JEONG , Hyun Sang KWAK , Seong Hwan LEE
IPC分类号： H01L23/552 , H01L23/13 , H01L23/498 , H01L23/538
CPC分类号： H01L23/552 , H01L23/13 , H01L23/49822 , H01L23/5385 , H01L24/13 , H01L24/16 , H01L25/0655 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13147 , H01L2224/16227 , H01L2924/014
摘要： A printed circuit board includes a substrate portion including a first insulating layer, a first wiring layer disposed on or within the first insulating layer, and a cavity penetrating through at least a portion of the first insulating layer; a connection structure disposed within the cavity of the substrate portion, and including a second insulating layer, a second wiring layer disposed on or within the second insulating layer, and a metal layer disposed on a lower surface and a side surface of the second insulating layer, wherein the metal layer is disposed on an outermost side of the connection structure.
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公开(公告)号：US20240332134A1
公开(公告)日：2024-10-03
申请号：US18193182
申请日：2023-03-30
申请人： Intel Corporation
发明人： Liang He , Jung Kyu Han , Gang Duan
IPC分类号： H01L23/495 , H01L21/768 , H01L23/00 , H01L23/15 , H01L23/528 , H01L23/532
CPC分类号： H01L23/49513 , H01L21/76898 , H01L23/15 , H01L23/5283 , H01L23/53228 , H01L24/03 , H01L24/06 , H01L24/11 , H01L24/14 , H01L2224/05147 , H01L2224/06131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131
摘要： Methods and apparatus to mitigate electromigration are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, a contact pad at least partially extending though or positioned on the dielectric substrate, the contact pad including copper, and a metal interconnect coupled to the contact pad, the interconnect including indium.
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公开(公告)号：US20240321851A1
公开(公告)日：2024-09-26
申请号：US18506346
申请日：2023-11-10
发明人： CHOONGBIN YIM , Jongkook Kim , Chengtar Wu
CPC分类号： H01L25/18 , H01L21/568 , H01L24/05 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/73 , H01L24/80 , H01L24/83 , H01L24/92 , H01L24/95 , H01L25/50 , H10B80/00 , H01L2224/0557 , H01L2224/05611 , H01L2224/05616 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/08145 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/19 , H01L2224/214 , H01L2224/215 , H01L2224/32145 , H01L2224/73204 , H01L2224/80006 , H01L2224/80357 , H01L2224/80379 , H01L2224/80896 , H01L2224/83005 , H01L2224/83862 , H01L2224/92125 , H01L2224/95001 , H01L2924/01013 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/0504 , H01L2924/05442 , H01L2924/059
摘要： A semiconductor package includes: a redistribution layer structure; a first semiconductor die and a second semiconductor die disposed on the redistribution layer structure; a bridge die disposed on the first semiconductor die and the second semiconductor die and that electrically connects the first semiconductor die and the second semiconductor die to each other; and a molding material disposed on the redistribution layer structure and that molds of the first semiconductor die, the second semiconductor die, and the bridge die. A bottom surface of the first semiconductor die and a bottom surface of the second semiconductor die are coplanar with an upper surface of the redistribution layer structure.
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公开(公告)号：US20240321800A1
公开(公告)日：2024-09-26
申请号：US18444786
申请日：2024-02-19
申请人： E Ink Holdings Inc.
发明人： Wenchuan Wang , Kuang-Heng Liang , Wen-Yu Kuo , Yen-Ze Huang , Jen-Shiun Huang
IPC分类号： H01L23/00 , G02B26/00 , G02F1/167 , G02F1/1676 , G02F1/1677
CPC分类号： H01L24/16 , G02B26/005 , G02F1/1676 , G02F1/1677 , H01L24/05 , H01L24/13 , G02F1/167 , H01L24/14 , H01L2224/05541 , H01L2224/05555 , H01L2224/13007 , H01L2224/13013 , H01L2224/13014 , H01L2224/13139 , H01L2224/13147 , H01L2224/14051 , H01L2224/14155 , H01L2224/16237 , H01L2924/1426
摘要： A display device includes a driving circuit substrate, a display layer, an opposite substrate, and a conducting structure. The driving circuit substrate includes a first substrate and a driving circuit layer disposed on the first substrate. The driving circuit layer includes a display region, a peripheral region at the periphery of the display region, and a conducting pad located between the peripheral region and an edge of the first substrate. The opposite substrate includes a second substrate and an opposite electrode layer disposed on the second substrate. The display layer is located between the opposite electrode layer and the driving circuit layer. A conductive member of the conducting structure is connected between the conducting pad and the opposite electrode layer. The conducting structure has a first width. The peripheral region has a second width. The first width is less than or equal to 2.5 times the second width.
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公开(公告)号：US20240312939A1
公开(公告)日：2024-09-19
申请号：US18674950
申请日：2024-05-27
发明人： MING-HO TSAI , JYUN-HONG CHEN , CHUN-CHEN LIU , YU-NU HSU , PENG-REN CHEN , WEN-HAO CHENG , CHI-MING TSAI
IPC分类号： H01L23/00
CPC分类号： H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/11462 , H01L2224/11618 , H01L2224/117 , H01L2224/11849 , H01L2224/13026 , H01L2224/13147 , H01L2224/1403
摘要： A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.
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公开(公告)号：US20240312920A1
公开(公告)日：2024-09-19
申请号：US18374310
申请日：2023-09-28
发明人： Keunho CHOI
IPC分类号： H01L23/538 , H01L23/00 , H01L25/18 , H10B80/00
CPC分类号： H01L23/5386 , H01L24/16 , H01L25/18 , H10B80/00 , H01L23/3128 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/13 , H01L24/17 , H01L24/32 , H01L24/33 , H01L24/73 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/06181 , H01L2224/08145 , H01L2224/08225 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/3303 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2924/014 , H01L2924/1431 , H01L2924/1432 , H01L2924/1433 , H01L2924/1436 , H01L2924/1437 , H01L2924/1438
摘要： A semiconductor package includes: a first redistribution structure having a structure including at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip disposed on the first redistribution structure; a second semiconductor chip disposed on the first redistribution structure; and bumps disposed between the first redistribution structure and the first semiconductor chip and between the first redistribution structure and the second semiconductor chip, wherein the at least one first redistribution layer includes a detour redistribution line disposed so that a portion of the detour redistribution line overlaps a space between the first and second semiconductor chips, and the detour redistribution line circuitously extends across the space between the first and second semiconductor chips so as not to overlap a stress concentration region partially overlapping a portion of the space between the first and second semiconductor chips, or extends into the stress concentration region.
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公开(公告)号：US20240312919A1
公开(公告)日：2024-09-19
申请号：US18120910
申请日：2023-03-13
申请人： Intel Corporation
发明人： Pezhman MONADGEMI
IPC分类号： H01L23/538 , H01L25/00 , H01L25/065
CPC分类号： H01L23/5386 , H01L25/0655 , H01L25/50 , H01L23/5381 , H01L24/13 , H01L24/16 , H01L2224/13147 , H01L2224/16225 , H01L2924/1432 , H01L2924/1434
摘要： Embodiments disclosed herein include a multi-die module. In an embodiment, the multi-die module comprises an interposer, where the interposer comprises a first region and a second region. In an embodiment, the first region is spaced apart from the second region by a saw street. In an embodiment, a first die is over the interposer, where the first die is positioned over the saw street. In an embodiment, a second die is adjacent to a first end of the first die, and a third die is adjacent to a second end of the first die opposite from the first end.
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