公开(公告)号：US20240312924A1

公开(公告)日：2024-09-19

申请号：US18122250

申请日：2023-03-16

申请人： Intel Corporation

发明人： Shishir Deshpande ,  Jung Kyu Han ,  Gang Duan ,  Srinivas Pietambaram

IPC分类号： H01L23/544

CPC分类号： H01L23/544 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2223/54426 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

摘要： Microelectronic devices, systems, and techniques are disclosed having package substrate land side fiducial structures that are readily distinguishable from adjacent interconnect structures during registration of the land side of the package substrate. The fiducial structure includes a ring shape, a double ring shape, a donut shape, a triangular shape, an H-shape, or an I-shape in contrast to the circular, square, or rectangular shape of the adjacent interconnect structure. The fiducial structure shape may also have a different size relative to the interconnect structure shape.

公开(公告)号：US20240213198A1

公开(公告)日：2024-06-27

申请号：US18087517

申请日：2022-12-22

申请人： Intel Corporation

发明人： Liang He ,  Yue Deng ,  Gang Duan ,  Jung Kyu Han ,  Ali Lehaf ,  Srinivas Pietambaram

IPC分类号： H01L23/00 ,  H01L23/538

CPC分类号： H01L24/13 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/13541 ,  H01L2224/1358 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13684 ,  H01L2224/16013 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841

摘要： An electronic package comprises a first die having at least one first interconnect with solder over or under a first metal feature. A second die has at least one second interconnect to the first die, each second interconnect comprising a second metal feature comprising copper, solder over or under the second metal feature, and a layer between the solder and the second metal feature, wherein the layer comprises iron and has a different material than material of the first interconnect.

公开(公告)号：US20240332134A1

公开(公告)日：2024-10-03

申请号：US18193182

申请日：2023-03-30

申请人： Intel Corporation

发明人： Liang He ,  Jung Kyu Han ,  Gang Duan

IPC分类号： H01L23/495 ,  H01L21/768 ,  H01L23/00 ,  H01L23/15 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/49513 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/5283 ,  H01L23/53228 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/05147 ,  H01L2224/06131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131

摘要： Methods and apparatus to mitigate electromigration are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, a contact pad at least partially extending though or positioned on the dielectric substrate, the contact pad including copper, and a metal interconnect coupled to the contact pad, the interconnect including indium.

公开(公告)号：US11955448B2

公开(公告)日：2024-04-09

申请号：US16880483

申请日：2020-05-21

申请人： Intel Corporation

发明人： Jung Kyu Han ,  Hongxia Feng ,  Xiaoying Guo ,  Rahul N. Manepalli

IPC分类号： H01L23/00 ,  H01L23/538

CPC分类号： H01L24/14 ,  H01L23/5381 ,  H01L24/16 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2924/381

摘要： Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate and a bridge substrate embedded in the package substrate. In an embodiment, first pads are over the package substrate, where the first pads have a first pitch, and second pads are over the bridge substrate, where the second pads have a second pitch that is smaller than the first pitch. In an embodiment, a barrier layer is over individual ones of the second pads. In an embodiment, reflown solder is over individual ones of the first pads and over individual ones of the second pads. In an embodiment, a first standoff height of the reflown solder over the first pads is equal to a second standoff height of the reflown solder over the second pads.

公开(公告)号：US20230317642A1

公开(公告)日：2023-10-05

申请号：US17707523

申请日：2022-03-29

申请人： Intel Corporation

发明人： Numair Ahmed ,  Cary Kuliasha ,  Kyu Oh Lee ,  Jung Kyu Han

IPC分类号： H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L21/48

CPC分类号： H01L23/645 ,  H01L23/49827 ,  H01L21/486 ,  H01L28/10 ,  H01L23/49838

摘要： A substrate for an electronic device may include a core. The substrate may include a passive electronic component. For instance, the substrate may include a continuous layer of molding material encapsulating the passive electronic component within the core. One or more through vias may extend between a first surface of the core and a second surface of the core. The substrate may include one or more layers coupled with the core. One or more component terminals may facilitate electrical communication between the passive electronic component and one or more of the first layer or the second layer.

公开(公告)号：US20240213163A1

公开(公告)日：2024-06-27

申请号：US18089417

申请日：2022-12-27

申请人： Intel Corporation

发明人： Jung Kyu Han

IPC分类号： H01L23/535 ,  H01L23/00 ,  H01L23/538 ,  H01L23/544 ,  H01L23/66 ,  H01L25/065

CPC分类号： H01L23/535 ,  H01L23/5381 ,  H01L23/5386 ,  H01L23/544 ,  H01L23/66 ,  H01L24/16 ,  H01L24/32 ,  H01L25/0655 ,  H01L2224/165 ,  H01L2224/32225

摘要： An electronic device and associated methods are disclosed. In one example, the electronic device includes vertical connections with a layer including tin between the vertical connections and conductive traces. In selected examples, a layer including tin is used in conjunction with other interface layers. In selected examples, a layer including tin is used in all vertical connections.

公开(公告)号：US11935857B2

公开(公告)日：2024-03-19

申请号：US17952080

申请日：2022-09-23

申请人： Intel Corporation

发明人： Kristof Darmawaikarta ,  Robert May ,  Sashi Kandanur ,  Sri Ranga Sai Boyapati ,  Srinivas Pietambaram ,  Steve Cho ,  Jung Kyu Han ,  Thomas Heaton ,  Ali Lehaf ,  Ravindranadh Eluri ,  Hiroki Tanaka ,  Aleksandar Aleksov ,  Dilan Seneviratne

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522

CPC分类号： H01L24/17 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/11 ,  H01L2924/01029 ,  H01L2924/0105

摘要： Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

公开(公告)号：US11488918B2

公开(公告)日：2022-11-01

申请号：US16177022

申请日：2018-10-31

申请人： Intel Corporation

发明人： Kristof Darmawaikarta ,  Robert May ,  Sashi Kandanur ,  Sri Ranga Sai Boyapati ,  Srinivas Pietambaram ,  Steve Cho ,  Jung Kyu Han ,  Thomas Heaton ,  Ali Lehaf ,  Ravindranadh Eluri ,  Hiroki Tanaka ,  Aleksandar Aleksov ,  Dilan Seneviratne

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768

摘要： Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

公开(公告)号：US11923312B2

公开(公告)日：2024-03-05

申请号：US16366661

申请日：2019-03-27

申请人： Intel Corporation

发明人： Bai Nie ,  Gang Duan ,  Srinivas Pietambaram ,  Jesse Jones ,  Yosuke Kanaoka ,  Hongxia Feng ,  Dingying Xu ,  Rahul Manepalli ,  Sameer Paital ,  Kristof Darmawikarta ,  Yonggang Li ,  Meizi Jiao ,  Chong Zhang ,  Matthew Tingey ,  Jung Kyu Han ,  Haobo Chen

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC分类号： H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/214 ,  H01L2924/3511 ,  H01L2924/381

摘要： A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

公开(公告)号：US20230197543A1

公开(公告)日：2023-06-22

申请号：US17557142

申请日：2021-12-21

申请人： Intel Corporation

发明人： Liang He ,  Yue Deng ,  Jung Kyu Han ,  Gang Duan

IPC分类号： H01L23/29 ,  H01L23/18

CPC分类号： H01L23/291 ,  H01L23/18 ,  H01L23/298

摘要： Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface with conductive contacts, in a first layer; a first material surrounding the first die and extending along a thickness of the first die from the second surface, and wherein the first material includes first particles having an average diameter between 200 and 500 nanometers; a second material surrounding the first die and extending along the thickness of the first die from the first surface, and wherein the second material includes second particles having an average diameter between 0.5 and 12 microns; an interface portion, between the first and second materials, including the first and second particles; and a second die, in a second layer on the first layer, electrically coupled to the conductive contacts on the first die.