公开(公告)号：US12300620B2

公开(公告)日：2025-05-13

申请号：US18367285

申请日：2023-09-12

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Tarek Ibrahim ,  Kristof Darmawikarta ,  Rahul N. Manepalli ,  Debendra Mallik ,  Robert L. Sankman

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065

Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.

公开(公告)号：US20240222257A1

公开(公告)日：2024-07-04

申请号：US18089801

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Yiqun Bai ,  Dingying Xu ,  Bai Nie ,  Kyle Jordan Arrington ,  Ziyin Lin ,  Rahul N. Manepalli ,  Brandon C. Marin ,  Jeremy D. Ecton

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L23/49894 ,  H01L21/481 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/15

Abstract: A substrate for an electronic system includes a glass core layer. The glass core layer includes a first surface and a second surface opposite the first surface; and at least one through-glass via (TGV) extending through the glass core layer from the first surface to the second surface. The TGV includes an opening filled with an electrically conductive material; and a via liner including a sidewall material disposed on a sidewall of the opening between the glass of the glass core layer and the electrically conductive material, wherein the sidewall material includes carbon.

公开(公告)号：US11862619B2

公开(公告)日：2024-01-02

申请号：US16649923

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Robert Alan May ,  Kristof Darmawikarta ,  Hiroki Tanaka ,  Rahul N. Manepalli ,  Sri Ranga Sai Boyapati

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49866 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0652 ,  H01L24/14 ,  H01L2224/1403

Abstract: Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.

公开(公告)号：US20230093186A1

公开(公告)日：2023-03-23

申请号：US17479871

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Tarek A. Ibrahim ,  Rahul N. Manepalli ,  Sairam Agraharam ,  Xiaoxuan Sun

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a semiconductor device. In selected examples, the semiconductor device may include two semiconductor dies, a redistribution layer, an interconnect bridge coupled between the two semiconductor dies and located vertically between the two semiconductor dies and the redistribution layer, and a metallic connection passing through the redistribution layer and coupled to one or more of the two semiconductor dies in a solder-free connection.

公开(公告)号：US20210391232A1

公开(公告)日：2021-12-16

申请号：US17459993

申请日：2021-08-27

Applicant: INTEL CORPORATION

Inventor： Rahul Jain ,  Kyu Oh Lee ,  Siddharth K. Alur ,  Wei-Lun K. Jen ,  Vipul V. Mehta ,  Ashish Dhall ,  Sri Chaitra J. Chavali ,  Rahul N. Manepalli ,  Amruthavalli P. Alur ,  Sai Vadlamani

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L23/498

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210111088A1

公开(公告)日：2021-04-15

申请号：US16464547

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Rahul Jain ,  Kyu Oh Lee ,  Siddharth K. Alur ,  Wei-Lun K. Jen ,  Vipul V. Mehta ,  Ashish Dhall ,  Sri Chaitra J. Chavali ,  Rahul N. Manepalli ,  Amruthavalli P. Alur ,  Sai Vadlamani

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210066190A1

公开(公告)日：2021-03-04

申请号：US17096781

申请日：2020-11-12

Applicant: Intel Corporation

Inventor： Srinivas Venkata Ramanuja Pietambaram ,  Rahul N. Manepalli

IPC: H01L23/522 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00

Abstract: Disclosed is an embedded multi-die interconnect bridge (EMIB) substrate. The EMIB substrate can comprise an organic substrate, a bridge embedded in the organic substrate and a plurality of routing layers. The plurality of routing layers can be embedded within the bridge. Each routing layer can have a plurality of traces. Each of the plurality of routing layers can have a coefficient of thermal expansion (CTE) that varies from an adjacent routing layer.

公开(公告)号：US09716084B2

公开(公告)日：2017-07-25

申请号：US15208502

申请日：2016-07-12

Applicant: INTEL CORPORATION

Inventor： Digvijay A. Raorane ,  Yonggang Li ,  Rahul N. Manepalli ,  Javier Soto Gonzalez

IPC: H01L25/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L21/683 ,  H01L23/522 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/8385 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/40501 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00 ,  H01L2924/014

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US09458283B2

公开(公告)日：2016-10-04

申请号：US14746750

申请日：2015-06-22

Applicant: INTEL CORPORATION

Inventor： Dingying Xu ,  Nisha Ananthakrishnan ,  Hong Dong ,  Rahul N. Manepalli ,  Nachiket R. Raravikar ,  Gregory S. Constable

IPC: C08G77/04 ,  C08L63/00 ,  B32B27/38 ,  C08G59/02 ,  C08L23/08 ,  H01L21/56 ,  H01L23/29 ,  C08G59/32 ,  C08G59/38 ,  C07F7/08 ,  H01L23/00

CPC classification number: C08G59/02 ,  C07F7/0838 ,  C08G59/3254 ,  C08G59/38 ,  C08L23/0884 ,  H01L21/563 ,  H01L23/293 ,  H01L24/16 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3512 ,  Y10T428/31515 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed.

公开(公告)号：US20150171067A1

公开(公告)日：2015-06-18

申请号：US14636016

申请日：2015-03-02

Applicant: INTEL CORPORATION

Inventor： Digvijay A. Raorane ,  Yonggang Li ,  Rahul N. Manepalli ,  Javier Soto Gonzalez

IPC: H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/4846 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05169 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/8385 ,  H01L2224/9222 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/40501 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00 ,  H01L2924/014

Abstract: Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及具有多个管芯的三维（3D）集成的集成电路（IC）封装组件，以及包含这种3D IC封装组件的相应制造方法和系统。 可以在诸如微处理器管芯的第一管芯上形成无凸起的堆积层（BBUL）封装衬底。 可以使用激光辐射在模具背面膜中形成开口，以暴露第一裸片背面的TSV焊盘。 诸如存储器管芯堆叠的第二管芯可以通过在第一和第二管芯的对应TSV之间形成的管芯互连而耦合到第一管芯。 可以施加底部填充材料以填充第一和第二管芯之间的任何剩余间隙中的一些或全部，和/或可以在第二管芯和/或封装衬底上施加密封剂。 可以描述和/或要求保护其他实施例。