公开(公告)号：US12027466B2

公开(公告)日：2024-07-02

申请号：US17026703

申请日：2020-09-21

申请人： Intel Corporation

发明人： Jeremy D. Ecton ,  Aleksandar Aleksov ,  Brandon C. Marin ,  Yonggang Li ,  Leonel Arana ,  Suddhasattwa Nad ,  Haobo Chen ,  Tarek Ibrahim

IPC分类号： H01L23/538 ,  H01L21/768 ,  H05K1/11

CPC分类号： H01L23/5386 ,  H01L21/76838 ,  H01L23/5385 ,  H05K1/11

摘要： Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.

公开(公告)号：US20240186250A1

公开(公告)日：2024-06-06

申请号：US18061188

申请日：2022-12-02

申请人： Intel Corporation

发明人： Jeremy D. Ecton ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Tarek A. Ibrahim ,  Suddhasattwa Nad ,  Gang Duan ,  Haobo Chen ,  Hiroki Tanaka

IPC分类号： H01L23/538 ,  H01L21/48

CPC分类号： H01L23/5381 ,  H01L21/486 ,  H01L23/5384 ,  H01L23/5386

摘要： A microelectronic assembly includes a substrate comprising: a panel including glass and defining an opening therein; an interconnect bridge (IB) in the opening and including interconnect pathways and IB through vias (IBTVs); and electrically conductive structures at a lower surface of the substrate to electrically couple the substrate to another component, at least some of the electrically conductive structures coupled to the IBTVs to form respective vertical electrical connections between the lower surface of the substrate and an upper surface of the substrate; and an electronic component (EC) layer on the upper surface of the substrate, the EC layer including a first active EC (AEC) and a second AEC electrically coupled to one another through the interconnect pathways, at least one of the first AEC or the second AECs further electrically coupled to one or more of the at least some of the electrically conductive structures.

公开(公告)号：US20240162157A1

公开(公告)日：2024-05-16

申请号：US17988051

申请日：2022-11-16

申请人： Intel Corporation

发明人： Jeremy D. Ecton ,  Brandon Christian Marin ,  Aleksandar Aleksov ,  Srinivas V. Pietambaram ,  Haobo Chen

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/15 ,  H01L23/498

CPC分类号： H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L25/0655

摘要： A bumpless hybrid organic glass interposer. One or more high density pattern (HDP) routing layers are placed on a functional, thin, carrier, separate from the intended organic substrate patch or package. The HDP layer(s) is/are then attached to the substrate package. The interposers achieve electrical connections between the HDP layer and underlying routing layer of the substrate package by utilizing a self-align dry etch process through landing pads connected to the HDP routing.

公开(公告)号：US20240079335A1

公开(公告)日：2024-03-07

申请号：US17939824

申请日：2022-09-07

申请人： Intel Corporation

发明人： Jeremy D. Ecton ,  Brandon Christian Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L23/5381 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/08 ,  H01L25/0655 ,  H01L2224/08225

摘要： In one embodiment, an integrated circuit device includes a first layer having input/output (IO) hub circuitry to interconnect a plurality of integrated circuit dies, and a second layer having a plurality of integrated circuit dies electrically connected to the IO hub circuitry. The first layer may include glass, and the IO hub circuitry may be in a die embedded within the first layer. The integrated circuit dies may be electrically connected to the IO hub circuitry through an interposer.

公开(公告)号：US20230395445A1

公开(公告)日：2023-12-07

申请号：US17833650

申请日：2022-06-06

申请人： Intel Corporation

发明人： Srinivas V. Pietambaram ,  Kristof Darmawikarta ,  Tarek A. Ibrahim ,  Jeremy D. Ecton ,  Brandon Christian Marin ,  Gang Duan ,  Suddhasattwa Nad ,  Yi Yang ,  Benjamin T. Duong ,  Junxin Wang ,  Sameer R. Paital

IPC分类号： H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H05K1/03 ,  H05K3/40

CPC分类号： H01L23/15 ,  H01L23/49827 ,  H01L21/486 ,  H05K1/0306 ,  H05K3/4061

摘要： In one embodiment, a substrate includes a glass core layer defining a plurality of holes between a first side of the glass core layer and a second side of the glass core layer opposite the first side and a conductive metal inside the holes of the glass core layer. The conductive metal electrically couples the first side of the glass core layer and the second side of the glass core layer. The substrate also includes a dielectric material between the conductive metal and the inside surfaces of the holes of the glass core layer.

公开(公告)号：US11721631B2

公开(公告)日：2023-08-08

申请号：US17752717

申请日：2022-05-24

申请人： Intel Corporation

发明人： Jeremy D. Ecton ,  Hiroki Tanaka ,  Oscar Ojeda ,  Arnab Roy ,  Vahidreza Parichehreh ,  Leonel R. Arana ,  Chung Kwang Tan ,  Robert A. May

IPC分类号： H01L23/538 ,  H01L21/48

CPC分类号： H01L23/5381 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386

摘要： Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US20200312793A1

公开(公告)日：2020-10-01

申请号：US16369708

申请日：2019-03-29

申请人： Intel Corporation

发明人： Brandon C. Marin ,  Shivasubramanian Balasubramanian ,  Rahul Jain ,  Praneeth Akkinepally ,  Jeremy D. Ecton

IPC分类号： H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L49/02

摘要： A substrate for an electronic device may include a first layer, a second layer, and may include a third layer. The first layer may include a capacitive material, and the capacitive material may be segmented into a first section, and a second section. Each of the first section and the second section may include a first surface and a second surface. The second layer may include a first conductor. The third layer may include a second conductor. The first surface of the second section of capacitive material may be directly coupled to the first conductor. The second surface of the second section of the capacitive material may be directly coupled to the second conductor. A first filler region may include a dielectric material and the first filler region may be located in a first gap between the first section of capacitive material and the second section of capacitive material.

公开(公告)号：US20240203806A1

公开(公告)日：2024-06-20

申请号：US18085291

申请日：2022-12-20

申请人： Intel Corporation

发明人： Bohan Shan ,  Bai Nie ,  Leonel R. Arana ,  Dingying XU ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Jeremy D. Ecton ,  Haobo Chen ,  Bin Mu

IPC分类号： H01L23/15 ,  C03C17/00 ,  C03C17/06 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L23/15 ,  C03C17/004 ,  C03C17/06 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  C03C2217/253 ,  C03C2218/365

摘要： An electronic device, including layers, formed from a material that can remain substantially constant in structure, such as glass. The layer can be preformed with through glass vias that support at least one electrically conductive interconnect. The through glass via can have an edge region that can be substantially coplanar with an exposed surface of the layer.

公开(公告)号：US20240186270A1

公开(公告)日：2024-06-06

申请号：US18074253

申请日：2022-12-02

申请人： Intel Corporation

发明人： Srinivas V. Pietambaram ,  Claudio A. Alvarez Barros ,  Beomseok Choi ,  Gang Duan ,  Jeremy D. Ecton ,  Brandon Christian Marin ,  Suddhasattwa Nad ,  Hiroki Tanaka

IPC分类号： H01L23/64 ,  H01F10/32 ,  H01L21/48 ,  H01L23/498

CPC分类号： H01L23/645 ,  H01F10/3272 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/0655

摘要： A microelectronic structure, a semiconductor package, an IC device assembly, and a method. The structure includes a core layer including an electrically non-conductive material; electrically conductive through core vias (TCVs) through the core layer; a dielectric layer on the core layer with electrically conductive structures extending therethrough and electrically coupled to the TCVs; and a magnetic inductor (MI) within at least one of the core layer or the build-up layer and including an antiferromagnetic (AF) structure. The AF structure includes a first ferromagnetic (FM) layer; an exchange coupling (EC) layer on the first FM layer and including a non-magnetic metal material; a second FM layer on the EC layer, the EC layer between the first FM layer and the second FM layer; and a pinning (P) layer including manganese and at least one of platinum or iridium, the second FM layer between the EC layer and the P layer.

公开(公告)号：US20240112972A1

公开(公告)日：2024-04-04

申请号：US17958002

申请日：2022-09-30

申请人： Intel Corporation

发明人： Hiroki Tanaka ,  Robert Alan May ,  Kristof Darmawikarta ,  Bai Nie ,  Brandon C. Marin ,  Jeremy D. Ecton ,  Srinivas Venkata Ramanuja Pietambaram ,  Changhua Liu

IPC分类号： H01L23/15 ,  G02B6/42 ,  G02B6/43

CPC分类号： H01L23/15 ,  G02B6/4204 ,  G02B6/4259 ,  G02B6/426 ,  G02B6/43

摘要： Disclosed herein are microelectronics package architectures utilizing photo-integrated glass interposers and photonic integrated glass layers and methods of manufacturing the same. The microelectronics packages may include an organic substrate, a photonic integrated glass layer, and a glass interpose. The organic substrate may define through substrate vias. The photonic integrated glass layer may be attached to the organic substrate. The photonic integrated glass layer may include photo detectors. The glass interposer may be attached to the organic substrate. The glass interposer may define through glass vias in optical communication with the photo detectors.