公开(公告)号：US20240363458A1

公开(公告)日：2024-10-31

申请号：US18309408

申请日：2023-04-28

Applicant: Joon Bu Park

Inventor： Joon Bu Park

IPC: H01L23/15 ,  H01L23/14 ,  H01L23/29 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/15 ,  H01L23/147 ,  H01L23/291 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06565 ,  H01L2225/06589

Abstract: A circuit chip includes a first body having a negative Poisson's ratio; a second body having a positive Poisson's ratio, wherein the first body and the second body are stacked on one another and thermally coupled to one another; and a first integrated circuit embedded in the second body.

公开(公告)号：US20240360027A1

公开(公告)日：2024-10-31

申请号：US18682636

申请日：2022-07-29

Applicant: NIPPON ELECTRIC GLASSS CO., LTD.

Inventor： Miyako TAKEDA

IPC: C03C3/091 ,  C03C4/00 ,  H01L21/02 ,  H01L23/15

CPC classification number: C03C3/091 ,  C03C4/0085 ,  H01L21/02164 ,  H01L23/15

Abstract: A support glass substrate of the present invention is a support glass substrate for supporting a substrate to be processed, the support glass substrate including, as a glass composition, in terms of mol %, 50% to 80% of SiO2, 0% to 25% of Al2O3, 5.5% to 20% of B2O3, 0% to 5% of Li2O+Na2O+K2O, 0% to 15% of MgO, 1% to 25% of CaO, 0% to 10% of SrO, and 0% to 10% of BaO, having a molar ratio (MgO+SrO+BaO)/CaO of 1.5 or less, and having an average coefficient of thermal expansion at from 30° C. to 380° C. of from 35×10−7/° C. to 60×10−7/° C.

公开(公告)号：US20240355752A1

公开(公告)日：2024-10-24

申请号：US18138440

申请日：2023-04-24

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/5386 ,  H01L21/486 ,  H01L23/15 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125

Abstract: Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core with a first surface and a second surface, where the core comprises a glass layer. In an embodiment, a first routing layer is over the first surface of the core, where the first routing layer comprises traces with a first width. In an embodiment, a second routing layer is over the second surface of the core, where the second routing layer comprises traces with a second width that is smaller than the first width.

公开(公告)号：US12125765B2

公开(公告)日：2024-10-22

申请号：US17638875

申请日：2020-08-19

Applicant: MITSUBISHI MATERIALS CORPORATION

Inventor： Nobuyuki Terasaki

IPC: H01L23/373 ,  B32B15/00 ,  B32B15/04 ,  B32B15/18 ,  B32B18/00 ,  C04B35/645 ,  C04B37/02 ,  H01L21/48 ,  H01L23/12 ,  H01L23/13 ,  H01L23/15 ,  H01L23/36 ,  H05K1/03 ,  H05K3/38

CPC classification number: H01L23/3735 ,  B32B15/00 ,  B32B15/04 ,  B32B15/043 ,  B32B15/18 ,  B32B18/00 ,  C04B35/645 ,  C04B37/021 ,  C04B37/026 ,  H01L21/4807 ,  H01L23/12 ,  H01L23/13 ,  C04B2235/6567 ,  C04B2235/6581 ,  C04B2235/72 ,  C04B2235/725 ,  C04B2237/12 ,  C04B2237/123 ,  C04B2237/126 ,  C04B2237/127 ,  C04B2237/343 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/407 ,  C04B2237/50 ,  C04B2237/52 ,  C04B2237/525 ,  C04B2237/60 ,  C04B2237/704 ,  H01L23/15 ,  H01L23/36 ,  H01L2224/32225 ,  H05K1/0306 ,  H05K3/38 ,  Y10T428/12576 ,  Y10T428/12597 ,  Y10T428/12611 ,  Y10T428/12618 ,  Y10T428/12882 ,  Y10T428/12903 ,  Y10T428/1291 ,  Y10T428/24967 ,  Y10T428/265

Abstract: A copper/ceramic bonded body is provided, including: a copper member made of copper or a copper alloy; and a ceramic member, the copper member and the ceramic member being bonded to each other, in which a total concentration of Al, Si, Zn, and Mn is 3 atom % or less when concentration measurement is performed by an energy dispersive X-ray analysis method at a position 1000 nm away from a bonded interface between the copper member and the ceramic member to a copper member side, assuming that a total value of Cu, Mg, Ti, Zr, Nb, Hf, Al, Si, Zn, and Mn is 100 atom %.

公开(公告)号：US20240332153A1

公开(公告)日：2024-10-03

申请号：US18129880

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Tchefor NDUKUM ,  Yonggang LI ,  Rengarajan SHANMUGAM ,  Darko GRUJICIC ,  Deniz TURAN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4864 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49866

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate and a seed layer over the substrate. In an embodiment, sidewalls of the seed layer are sloped. In an embodiment, the electronic package further comprises a feature over the seed layer, where the feature is electrically conductive.

公开(公告)号：US20240332132A1

公开(公告)日：2024-10-03

申请号：US18740523

申请日：2024-06-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jen-Chun Liao ,  Sung-Yueh Wu ,  Chien-Ling Hwang ,  Ching-Hua Hsieh

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/15 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a carrier substrate, a through substrate via (TSV), a first conductive pattern, and an encapsulated die. The TSV penetrates through the carrier substrate and includes a first portion and a second portion connected to the first portion, the first portion includes a first slanted sidewall with a first slope, the second portion includes a second slanted sidewall with a second slope, and the first slope is substantially milder than the second slope. The first conductive pattern is disposed on the carrier substrate and connected to the first portion of the TSV. The encapsulated die is disposed on the carrier substrate and electrically coupled to the TSV through the first conductive pattern.

公开(公告)号：US20240332100A1

公开(公告)日：2024-10-03

申请号：US18193172

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Pratyush Mishra ,  Marcel Wall ,  Sashi Kandanur ,  Pooya Tadayon ,  Srinivas Pietambaram ,  Benjamin Duong ,  Suddhasattwa Nad

IPC: H01L23/15 ,  H01F27/24 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L23/15 ,  H01F27/24 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5226

Abstract: Glass-integrated inductors in integrated circuit (IC) packages are disclosed. A disclosed IC package includes a glass layer having an aperture extending therethrough, and an inductor in the aperture, the inductor including a metal core extending through the aperture, the metal core electrically coupled to interconnects on opposite sides of the glass layer, and at least one of a ferrite or a magnetic alloy in the aperture and laterally surrounding the metal core.

公开(公告)号：US12107023B2

公开(公告)日：2024-10-01

申请号：US17473196

申请日：2021-09-13

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Keiichiro Matsuo ,  Izuru Komatsu ,  Haruka Yamamoto

IPC: H01L23/053 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/492

CPC classification number: H01L23/053 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/492 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48177

Abstract: A power module includes a base plate, a casing, a substrate unit, a terminal plate, a first resin layer, and a second resin layer. The substrate unit includes a substrate fixed on the base plate, a dam part, a semiconductor chip, a metal member, and a wire. The dam part is formed along an edge of the substrate. The wire includes an electrode plate connection portion, and a chip connection portion. The first resin layer is located inward of the dam part. The chip connection portion and the electrode plate connection portion are located inside the first resin layer. The second resin layer is located on the first resin layer. The upper surface of the metal member is located inside the second resin layer. An elastic modulus of the second resin layer is less than that of the first resin layer.

公开(公告)号：US20240321658A1

公开(公告)日：2024-09-26

申请号：US18680167

申请日：2024-05-31

Applicant: Amkor Technology Singapore Holding Pte. Ltd.

Inventor： Ji Young Chung ,  Dong Joo Park ,  Jin Seong Kim ,  Jae Sung Park ,  Se Hwan Hong

IPC: H01L23/15 ,  G06V40/13 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498

CPC classification number: H01L23/15 ,  G06V40/1329 ,  H01L24/48 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/4952 ,  H01L23/49805 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/02166 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48165 ,  H01L2224/48227 ,  H01L2224/48992 ,  H01L2224/48997 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15313 ,  H01L2924/181

Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate.

公开(公告)号：US12100761B2

公开(公告)日：2024-09-24

申请号：US17578259

申请日：2022-01-18

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Kimin Jun ,  Il-Seok Son ,  Donald W. Nelson

IPC: H01L29/78 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L29/417 ,  H01L23/15

CPC classification number: H01L29/78 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/49827 ,  H01L24/00 ,  H01L24/05 ,  H01L29/41791 ,  H01L23/145 ,  H01L23/15 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/0603 ,  H01L2224/16227

Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.