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    Dynamic logic built with stacked transistors sharing a common gate
    1.
    发明授权
    Dynamic logic built with stacked transistors sharing a common gate 有权

    公开(公告)号：US11282861B2

    公开(公告)日：2022-03-22

    申请号：US15774556

    申请日：2015-12-26

    Applicant: Intel Corporation

    Inventor： Donald W. Nelson ,  Rishabh Mehandru

    IPC: H01L23/538 ,  H01L27/12 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/06

    Abstract: A dynamic logic circuit including a first transistor within a first device stratum of a substrate; and a second transistor within a second device stratum of the substrate that is different from the first device stratum, wherein the first transistor and the second transistor share a common gate electrode. A method including disposing a second semiconductor body of a second transistor on a first semiconductor body of a first transistor in a first device stratum on a substrate, the second semiconductor body defining a second device stratum; and forming a common gate electrode on each of the semiconductor body and the second semiconductor body.

    Wrap-around source/drain method of making contacts for backside metals
    3.
    发明授权
    Wrap-around source/drain method of making contacts for backside metals 有权

    公开(公告)号：US11264493B2

    公开(公告)日：2022-03-01

    申请号：US15747423

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： Patrick Morrow ,  Kimin Jun ,  Il-Seok Son ,  Donald W. Nelson

    IPC: H01L29/78 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L29/417 ,  H01L23/15

    Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

    Method, device and system to provide capacitance for a dynamic random access memory cell
    4.
    发明授权
    Method, device and system to provide capacitance for a dynamic random access memory cell 有权

    公开(公告)号：US11049861B2

    公开(公告)日：2021-06-29

    申请号：US15747692

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： Aaron Lilak ,  Patrick Morrow ,  Rishabh Mehandru ,  Donald W. Nelson ,  Stephen M. Cea

    IPC: H01L27/108

    Abstract: Techniques and mechanisms to provide capacitance with a memory cell of an integrated circuit. In an embodiment, a transistor of the memory cell includes structures variously formed in or on a first side of a semiconductor substrate. After processing to form the transistor structures, thinning is performed to expose a second side of the semiconductor substrate, the second side opposite the first side. Processing in or on the exposed second side of the semiconductor substrate is subsequently performed to form in the semiconductor substrate a capacitor that extends to couple to one of the transistor structures. In another embodiment, the capacitor is coupled to accumulate charge based on activation of a channel of the transistor. The capacitor is further coupled to send charge from the memory cell via the second side.

    Ebeam align on the fly
    5.
    发明授权
    Ebeam align on the fly 有权

    公开(公告)号：US10290528B2

    公开(公告)日：2019-05-14

    申请号：US15122792

    申请日：2014-12-22

    Applicant: Intel Corporation

    Inventor： Yan A. Borodovsky ,  Donald W. Nelson ,  Mark C. Phillips

    IPC: G03F9/00 ,  H01L21/68 ,  H01L21/027 ,  H01J37/317 ,  H01L21/311

    Abstract: Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a method of real-time alignment of a wafer situated on a stage of an e-beam tool involves collecting backscattered electrons from an underlying patterned feature of the wafer while an e-beam column of the e-beam tool writes during scanning of the stage. The collecting is performed by an electron detector placed at the e-beam column bottom. The method also involves performing linear corrections of an alignment of the stage relative to the e-beam column based on the collecting.

    Metal on both sides with clock gated-power and signal routing underneath
    9.
    发明授权
    Metal on both sides with clock gated-power and signal routing underneath 有权

    公开(公告)号：US10658291B2

    公开(公告)日：2020-05-19

    申请号：US16227406

    申请日：2018-12-20

    Applicant: Intel Corporation

    Inventor： Donald W. Nelson ,  Patrick Morrow ,  Kimin Jun

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L29/78

    Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and contact points coupled to the second plurality of interconnects, the contact points operable for connection to an external source.

    Method for direct integration of memory die to logic die without use of thru silicon vias (TSV)
    10.
    发明授权
    Method for direct integration of memory die to logic die without use of thru silicon vias (TSV) 有权

    公开(公告)号：US10068874B2

    公开(公告)日：2018-09-04

    申请号：US15122630

    申请日：2014-06-16

    Applicant: Intel Corporation

    Inventor： Donald W. Nelson ,  M Clair Webb ,  Patrick Morrow ,  Kimin Jun

    IPC: H01L23/34 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

    Abstract: A method including forming a first substrate including an integrated circuit device layer disposed between a plurality of first interconnects and a plurality of second interconnects; coupling a second substrate including a memory device layer to the first substrate so that the memory device layer is juxtaposed to one of the plurality of first interconnects and the plurality of second interconnects; and removing a portion of the first substrate. An apparatus including a device layer including a plurality of circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects on a substrate; a memory device layer including a plurality of memory devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects; and contacts points coupled to one of ones of the first plurality of interconnects and ones of the second plurality of interconnects.

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