公开(公告)号：US20240355633A1

公开(公告)日：2024-10-24

申请号：US18762702

申请日：2024-07-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Yen Chen

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/3086 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3088 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

Abstract: A method includes forming an etching mask to cover a mandrel, a first spacer, and a second spacer, and the first spacer and the second spacer are in contact with opposing sidewalls of the mandrel. The etching mask is then patterned, and includes a first portion covering the first spacer, a second portion covering the second spacer, and a bridge portion connecting the first portion to the second portion. The bridge portion has first sidewalls. A first etching process is performed on the mandrel using the etching mask to define pattern, and after the first etching process, the mandrel includes a second bridge portion having second sidewalls vertically aligned to corresponding ones of the first sidewalls. After the mandrel is etched-through, a second etching process is performed to laterally recess the second bridge portion of the mandrel.

公开(公告)号：US12127385B2

公开(公告)日：2024-10-22

申请号：US17565738

申请日：2021-12-30

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Fujio Masuoka ,  Nozomu Harada

IPC: H01L21/768 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00 ,  H01L21/311

CPC classification number: H10B10/12 ,  H01L21/76816 ,  H01L29/4234 ,  H01L29/66666 ,  H01L29/7827 ,  H01L21/31116 ,  H01L21/31144

Abstract: In formation of an SRAM cell, a band-shaped contact hole C3 is formed that does not overlap, in plan view. N+ layers 32a, 32c, 32d, and 32f formed on and at outer peripheries of the top portions of Si pillars 6a, 6c, 6d, and 6f, that partly overlaps W layers 33b and 33e on P+ layers 32b and 32e connected to the top portions of Si pillars 6b and 6e, that is connected in both the X direction and the Y direction, and that extends in the Y direction. A power supply wiring metal layer Vdd that connects the P+ layers 32b and 32e through the contact hole C3 is formed. After formation of the power supply wiring metal layer Vdd, a word wiring metal layer WL is formed so as to be orthogonal to the power supply wiring metal layer Vdd in plan view.

公开(公告)号：US20240347346A1

公开(公告)日：2024-10-17

申请号：US18300954

申请日：2023-04-14

Applicant: Tokyo Electron Limited

Inventor： Minjoon PARK ,  Alec DORFNER ,  Matthew OCANA ,  Andrew METZ

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31116 ,  H01L21/31144 ,  H01L21/76816

Abstract: A method includes providing a semiconductor substrate having a first region and a second region. The method includes forming a stack of dielectric layers over the semiconductor substrate. The method includes patterning the stack to form first trenches over the first region and second trenches over the second region. The method further includes forming first conductive features having a first width in the first trenches and second conductive features having a second width in the second trenches, where the second width is less than the first width.

公开(公告)号：US20240339396A1

公开(公告)日：2024-10-10

申请号：US18745773

申请日：2024-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Han Wu ,  Cheng-Hsiung Tsai ,  Chih Wei Lu ,  Chung-Ju Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/7685 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L24/32 ,  H01L24/37 ,  H01L2924/181

Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

公开(公告)号：US12113063B2

公开(公告)日：2024-10-08

申请号：US18103210

申请日：2023-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Chih Wen ,  Han-Ting Tsai ,  Chung-Te Lin

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/822 ,  H01L23/522 ,  H01L23/525 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N70/00 ,  H10N70/20 ,  H01L21/8234 ,  H10K59/00

CPC classification number: H01L27/0688 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/525 ,  H10B61/22 ,  H10B63/30 ,  H10N50/01 ,  H10N70/011 ,  H10N70/20 ,  H10N70/231 ,  H01L21/823475 ,  H10K59/00

Abstract: A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

公开(公告)号：US12112979B2

公开(公告)日：2024-10-08

申请号：US17833839

申请日：2022-06-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yan-Jhi Huang ,  Yu-Yu Chen

IPC: H01L21/76 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76829 ,  H01L21/76877

Abstract: A method for manufacturing a semiconductor device includes forming a hard mask layer overlying a device layer of a semiconductor device, a mandrel underlayer over hard mask layer, and a mandrel layer over mandrel underlayer. The mandrel layer has a plurality of mandrel lines extending along a first direction. A plurality of openings are formed in mandrel underlayer extending in a second direction substantially perpendicular to first direction. A spacer layer is formed over mandrel underlayer and layer. Spacer layer fills plurality of openings in underlayer. Portions of spacer layer are removed to expose an upper surface of underlayer and mandrel layer, and mandrel layer is removed. By using remaining portions of spacer layer as a mask, underlayer and hard mask layer are removed, to form a hard mask pattern with first hard mask pattern lines extending along first direction and second hard mask pattern lines extending along second direction.

公开(公告)号：US20240332069A1

公开(公告)日：2024-10-03

申请号：US18190328

申请日：2023-03-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Han Chen ,  Shih-Yu Chang ,  Chien-Chih Chiu ,  Y.T. Chen ,  Da-Wei Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76832 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: A semiconductor interconnect structure includes a conductive line electrically coupled to an active semiconductor device, a first etch stop layer formed over the conductive line, a first dielectric layer formed over the first etch stop layer, a second etch stop layer formed over the first dielectric layer, a second dielectric layer formed over the second etch stop layer, and an interconnect structure electrically coupled to the via and extending through the first etch stop layer, the first dielectric layer, the second etch stop layer, and the second dielectric layer. The interconnect structure includes a via extending through the first etch stop layer, the second etch stop layer, and the first dielectric layer and a trench extending through the second dielectric layer.

公开(公告)号：US12107046B2

公开(公告)日：2024-10-01

申请号：US17597907

申请日：2019-07-31

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Gang Zhang ,  Zongliang Huo

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/535

Abstract: Provided is an L-shaped stepped word line structure including: L-shaped word line units, each including a long side extending in a second direction and arranged adjacent to a gate line slit, and a short side extending in a first direction. A word line terminal included in the short side is formed in a stepped stacked layer structure including stacked layer pairs formed of an insulating material, a region close to the gate line slit in a stacked layer of each stacked layer pair serves as a replacement metal region including a short side region surface/internal metal layer respectively located on a surface/in an interior. In a first direction, a length of the short side region surface metal layer is greater than that of the short side region internal metal layer, and the word line terminal corresponds to the short side region surface metal layer.

公开(公告)号：US12106963B2

公开(公告)日：2024-10-01

申请号：US18140425

申请日：2023-04-27

Applicant: Tessera LLC

Inventor： Sean D. Burns ,  Lawrence A. Clevenger ,  Matthew E. Colburn ,  Nelson M. Felix ,  Sivananda K. Kanakasabapathy ,  Christopher J. Penny ,  Roger A. Quon ,  Nicole A. Saulnier

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L21/027 ,  H01L21/28 ,  H01L21/31 ,  H10K71/20 ,  H10N70/00

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L21/0274 ,  H01L21/28123 ,  H01L21/31 ,  H01L21/76897 ,  H01L2224/0362 ,  H01L2224/11622 ,  H10K71/233 ,  H10N70/063

Abstract: A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

公开(公告)号：US12087693B2

公开(公告)日：2024-09-10

申请号：US17441217

申请日：2019-05-09

Applicant: Intel NDTM US LLC

Inventor： Daniel R. Lamborn ,  Chuan Sun ,  Qi Zhou

IPC: H10B43/50 ,  H01L21/768 ,  H01L23/528 ,  H01L23/535 ,  H10B41/50 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76895 ,  H01L23/5283 ,  H10B43/50 ,  H10B41/50 ,  H10B43/27

Abstract: Etch stops are disclosed for integrated circuit applications that have a set contacts of varying height, wherein there is a large height differential between the shortest and tallest contacts. In one example, an etch stop is provisioned over a 3D NAND memory staircase structure. The structure is then planarized with an insulator material that can be selectively etched with respect to the etch stop. Contact holes that land on corresponding wordlines of the staircase are etched. Due to the nature of the staircase, the holes vary in depth depending on which step of the staircase they land. The etch stop under the shallowest hole remains intact while the deepest hole is etched to completion. Once all holes have landed on the etch stop, a further etch selective to the insulator material is carried out to punch through the etch stop and expose underlying wordlines. Contacts are deposited into the holes.