公开(公告)号：US20240347346A1

公开(公告)日：2024-10-17

申请号：US18300954

申请日：2023-04-14

Applicant: Tokyo Electron Limited

Inventor： Minjoon PARK ,  Alec DORFNER ,  Matthew OCANA ,  Andrew METZ

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31116 ,  H01L21/31144 ,  H01L21/76816

Abstract: A method includes providing a semiconductor substrate having a first region and a second region. The method includes forming a stack of dielectric layers over the semiconductor substrate. The method includes patterning the stack to form first trenches over the first region and second trenches over the second region. The method further includes forming first conductive features having a first width in the first trenches and second conductive features having a second width in the second trenches, where the second width is less than the first width.