公开(公告)号：US20240355784A1

公开(公告)日：2024-10-24

申请号：US18758167

申请日：2024-06-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih-Han Huang ,  I-Nan Chen

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53209 ,  H01L24/33 ,  H01L24/83 ,  H01L25/50

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, the 3D IC comprises a first IC die comprising a first substrate, a first interconnect structure disposed over the first substrate, and a first through substrate via (TSV) disposed through the first substrate. The 3D IC further comprises a second IC die comprising a second substrate, a second interconnect structure disposed over the second substrate, and a second TSV disposed through the second substrate. The 3D IC further comprises a bonding structure arranged between back sides of the first IC die and the second IC die opposite to corresponding interconnect structures and bonding the first IC die and the second IC die. The bonding structure comprises conductive features disposed between and electrically connecting the first TSV and the second TSV.

公开(公告)号：US20240312971A1

公开(公告)日：2024-09-19

申请号：US18545341

申请日：2023-12-19

Applicant: AUO Corporation

Inventor： CHIH-TSUNG LEE

IPC: H01L25/16 ,  H01L23/528 ,  H01L23/532 ,  H10N39/00

CPC classification number: H01L25/167 ,  H01L23/5283 ,  H01L23/53209 ,  H10N39/00

Abstract: An electronic apparatus includes a component layer and a channel layer overlapping with each other. The component layer has a plurality of functional areas separated from each other and a connection area outside the functional areas. The component layer includes a plurality of electronic components disposed in at least some of the functional areas. The channel layer includes at least one stretchable layer, a plurality of first microfluidic channels and a first liquid conductor. The first microfluidic channels are disposed in the at least one stretchable layer, and extend through the functional areas and the connection area. The first liquid conductor is filled in the first microfluidic channels and is electrically connected to at least some of the electronic components. Each of the first microfluidic channels is provided with a buffer bag. A method of fabricating an electronic apparatus is also provided.

公开(公告)号：US20240304543A1

公开(公告)日：2024-09-12

申请号：US18668038

申请日：2024-05-17

Applicant: Intel Corporation

Inventor： Kevin Lin ,  Noriyuki Sato ,  Tristan Tronic ,  Michael Christenson ,  Christopher Jezewski ,  Jiun-Ruey Chen ,  James M. Blackwell ,  Matthew Metz ,  Miriam Reshotko ,  Nafees Kabir ,  Jeffery Bielefeld ,  Manish Chandhok ,  Hui Jae Yoo ,  Elijah Karpov ,  Carl Naylor ,  Ramanan Chebiam

IPC: H01L23/522 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/32139 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76843 ,  H01L23/5283 ,  H01L23/53209

Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

公开(公告)号：US20240297119A1

公开(公告)日：2024-09-05

申请号：US18573116

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Srikant Nekkanty ,  Karumbu Meyyappan ,  Andres Ramirez Macias ,  Zhe Chen ,  Jeffory L. Smalley ,  Zhichao Zhang ,  Steven A. Klein ,  Eric Erike

IPC: H01L23/532 ,  H01L23/32 ,  H01L23/40 ,  H01L23/498 ,  H01L23/528

CPC classification number: H01L23/53209 ,  H01L23/32 ,  H01L23/4093 ,  H01L23/49811 ,  H01L23/5283

Abstract: An electronic device (100, 800, 1000) and associated methods are disclosed. In one example, the electronic device (100, 800, 1000) includes an interconnect socket (102, 302, 402, 802, 1004, 1320, 1402, 1506) that includes a liquid metal. In selected examples, the interconnect socket (102, 302, 402) includes a resilient material spacer (130, 230, 330, 430) located between pins (110, 210, 310, 410) in an array of pins (110, 210, 310, 410). In selected examples, the electronic device (1000) includes configurations to aid in de-socketing.

公开(公告)号：US20240282580A1

公开(公告)日：2024-08-22

申请号：US18655124

申请日：2024-05-03

Applicant: Lam Research Corporation

Inventor： Xiaolan BA ,  Ruopeng DENG ,  Juwen GAO ,  Sanjay GOPINATH ,  Lawrence SCHLOSS

IPC: H01L21/285 ,  C23C16/04 ,  C23C16/14 ,  C23C16/455 ,  H01L21/768 ,  H01L23/532 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L21/28568 ,  C23C16/045 ,  C23C16/14 ,  C23C16/45527 ,  C23C16/45544 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/53209 ,  H01L23/53242 ,  H01L23/53257 ,  H10B41/27 ,  H10B43/27

Abstract: Described herein are methods and apparatuses for filling semiconductor substrate structures with conductive material. The methods involve depositing multi-layer bulk metal films in structures with one or more deposition conditions changed when transitioning from layer-to-layer. The methods result in high fill quality, high throughput, low precursor consumption, and low roughness. Multi-station chambers to perform the methods are also provided.

公开(公告)号：US12069866B2

公开(公告)日：2024-08-20

申请号：US17465792

申请日：2021-09-02

Applicant: Kepler Computing, Inc.

Inventor： Noriyuki Sato ,  Tanay Gosavi ,  Niloy Mukherjee ,  Amrita Mathuriya ,  Rajeev Kumar Dokania ,  Sasikanth Manipatruni

IPC: H10B53/30 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L49/02 ,  H03K19/185 ,  H10B53/10 ,  H10B53/40

CPC classification number: H10B53/30 ,  H01L21/76802 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/535 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H03K19/185 ,  H10B53/10

Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

公开(公告)号：US12062578B2

公开(公告)日：2024-08-13

申请号：US17838645

申请日：2022-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Lee ,  Chung-Ting Ko ,  Chen-Ming Lee ,  Mei-Yun Wang ,  Fu-Kai Yang

IPC: H01L27/01 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/532 ,  H01L27/088 ,  H01L27/12 ,  H01L29/66 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L23/53209 ,  H01L27/0886 ,  H01L29/66795 ,  H01L21/76805 ,  H01L21/76855 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41791

Abstract: A method for semiconductor fabrication includes providing a device structure having an isolation structure, a fin adjacent the isolation structure, gate structures over the fin and the isolation structure, one or more dielectric layers over the isolation structure and the fin and between the gate structures, a first contact hole over the fin, and a second contact hole over the isolation structure. The method further includes depositing a protection layer and treating it with a plasma so that the protection layer in the first contact hole and the protection layer in the second contact hole have different etch selectivity in an etching process; and etching the protection layer to etch through the protection layer on the bottom surface of the first contact hole without etching through the protection layer on the bottom surface of the second contact hole.

公开(公告)号：US12057492B2

公开(公告)日：2024-08-06

申请号：US18367292

申请日：2023-09-12

Applicant: Intel Corporation

Inventor： Tahir Ghani ,  Byron Ho ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H10N70/00 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H10B10/00 ,  H10B63/00 ,  H10N70/20 ,  H01L23/00

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

公开(公告)号：US12051592B2

公开(公告)日：2024-07-30

申请号：US17509314

申请日：2021-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Li Wang ,  Hung-Yi Huang ,  Yu-Yun Peng ,  Mrunal A. Khaderbad ,  Chia-Hung Chu ,  Shuen-Shin Liang ,  Keng-Chu Lin

IPC: H01L21/265 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/26586 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76895 ,  H01L23/53209 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/535

Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.

公开(公告)号：US12033889B2

公开(公告)日：2024-07-09

申请号：US18097418

申请日：2023-01-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hsin-Yen Huang ,  Ting-Ya Lo ,  Shao-Kuan Lee ,  Chi-Lin Teng ,  Cheng-Chin Lee ,  Hsiaokang Chang ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76841 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53295 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266

Abstract: An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first portion and a second portion adjacent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature. The structure further includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a support layer in contact with the first and second barrier layers. An air gap is located between the first and second barrier layers, and the dielectric layer and the support layer are exposed to the air gap.