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公开(公告)号：US12094511B1
公开(公告)日：2024-09-17
申请号：US17805665
申请日：2022-06-06
发明人： Rajeev Kumar Dokania , Mustansir Yunus Mukadam , Tanay Gosavi , James David Clarkson , Neal Reynolds , Amrita Mathuriya , Sasikanth Manipatruni
CPC分类号： G11C11/2275 , G11C11/221 , H10B53/30
摘要： A disturb mitigation scheme is described for a 1TnC or multi-element ferroelectric gain bit-cell where after writing to a selected capacitor of the bit-cell, a cure phase is initiated. Between the cure phase and the write phase, there may be zero or more cycles where the selected word-line, bit-line, and plate-lines are pulled-down to ground. The cure phase may occur immediately before the write phase. In the cure phase, the word-line is asserted again just like in the write phase. In the cure phase, the voltage on bit-line is inverted compared to the voltage on the bit-line in the write phase. By programming a value in a selected capacitor to be opposite of the value written in the write phase of that selected capacitor, time accumulation of disturb is negated. This allows to substantially zero out disturb field on the unselected capacitors of the same bit-cell and/or other unselected bit-cells.
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公开(公告)号：US20240276735A1
公开(公告)日：2024-08-15
申请号：US18448918
申请日：2023-08-12
发明人： Biswajeet Guha , Mauricio Manfrini , Noriyuki Sato , James David Clarkson , Abel Fernandez , Somilkumar J. Rathi , Niloy Mukherjee , Tanay Gosavi , Amrita Mathuriya , Rajeev Kumar Dokania , Sasikanth Manipatruni
CPC分类号： H10B53/30 , H01L24/05 , H01L24/08 , H01L24/80 , H01L2224/05541 , H01L2224/05557 , H01L2224/05686 , H01L2224/08145 , H01L2224/80931 , H01L2924/04941 , H01L2924/04953
摘要： A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.
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3.发明公开公开(公告)号：US20240276734A1
公开(公告)日：2024-08-15
申请号：US18448917
申请日：2023-08-12
发明人： Biswajeet Guha , Mauricio Manfrini , Noriyuki Sato , James David Clarkson , Abel Fernandez , Somilkumar J. Rathi , Niloy Mukherjee , Tanay Gosavi , Amrita Mathuriya , Rajeev Kumar Dokania , Sasikanth Manipatruni
CPC分类号： H10B53/20 , H01L28/55 , H01L28/91 , H01L28/92 , H01L29/40111 , H01L29/516 , H01L29/6684 , H01L29/78391 , H10B51/20
摘要： A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.
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公开(公告)号：US20240274651A1
公开(公告)日：2024-08-15
申请号：US18448852
申请日：2023-08-11
发明人： Biswajeet Guha , Mauricio Manfrini , Noriyuki Sato , James David Clarkson , Abel Fernandez , Somilkumar J. Rathi , Niloy Mukherjee , Tanay Gosavi , Amrita Mathuriya , Rajeev Kumar Dokania , Sasikanth Manipatruni
CPC分类号： H01L28/60 , H01L24/32 , H01L28/55 , H01L2224/32145
摘要： A method of fabricating a device comprises forming a multi-layer stack above a first substrate, where multi-layer stack includes a non-linear polar material. In at least one embodiment, method further includes forming a first conductive layer on multi-layer stack and annealing multi-layer stack. A transistor is formed above a second substrate. In at least one embodiment, method also includes forming a second conductive layer above electrode structure and bonding first conductive layer with second conductive layer. After bonding, method includes removing at least a portion of first substrate patterning multi-layer stack to form a memory device.
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公开(公告)号：US20240257854A1
公开(公告)日：2024-08-01
申请号：US18161808
申请日：2023-01-30
发明人： Rajeev Kumar Dokania , Mustansir Yunus Mukadam , Erik Unterborn , Pramod Kolar , Amrita Mathuriya , Debo Olaosebikan , Tanay Gosavi , Noriyuki Sato , Sasikanth Manipatruni
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C11/2255 , G11C11/2257 , G11C11/2259 , G11C11/2273
摘要： Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.
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公开(公告)号：US12029043B1
公开(公告)日：2024-07-02
申请号：US17552330
申请日：2021-12-15
发明人： Somilkumar J. Rathi , Noriyuki Sato , Niloy Mukherjee , Rajeev Kumar Dokania , Amrita Mathuriya , Tanay Gosavi , Pratyush Pandey , Jason Y. Wu , Sasikanth Manipatruni
IPC分类号： H10B53/30
CPC分类号： H10B53/30
摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.
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7.发明授权公开(公告)号：US12026034B1
公开(公告)日：2024-07-02
申请号：US17472330
申请日：2021-09-10
发明人： Amrita Mathuriya , Christopher B. Wilkerson , Rajeev Kumar Dokania , Debo Olaosebikan , Sasikanth Manipatruni
IPC分类号： G06F1/32 , G06F1/329 , H01L23/48 , H01L23/498 , H01L23/538 , G06N20/00
CPC分类号： G06F1/329 , H01L23/481 , H01L23/49816 , H01L23/49833 , H01L23/49838 , H01L23/5385 , H01L23/5386 , G06N20/00 , H01L2924/14335 , H01L2924/1438 , H01L2924/1441
摘要： A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.
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8.发明公开公开(公告)号：US20240211872A1
公开(公告)日：2024-06-27
申请号：US18358545
申请日：2023-07-25
发明人： Sasikanth Manipatruni , Niloy Mukherjee , Noriyuki Sato , Tanay Gosavi , Somilkumar J. Rathi , James David Clarkson , Rajeev Kumar Dokania , Debo Olaosebikan , Amrita Mathuriya
CPC分类号： G06Q10/087 , G06Q30/04 , G16C20/70
摘要： A method for monetizing ferroelectric process development is described. In at least one embodiment, the method comprises procuring a target material based on a model driven selection which is based on charge, mass and magnetic moment, and/or mass of the atomic constituents of the target material. The method further comprises applying the target material to a fabrication process to build a ferroelectric device. The method further comprises generating a notification indicative of procurement of the target material and application of the target material. The method further comprises electronically transmitting the notification to a customer, wherein the notification includes an invoice having a line item associated with a cost of the procuring of the target material and application of the target material.
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公开(公告)号：US12019492B1
公开(公告)日：2024-06-25
申请号：US17408326
申请日：2021-08-20
发明人： Amrita Mathuriya , Christopher B. Wilkerson , Rajeev Kumar Dokania , Debo Olaosebikan , Sasikanth Manipatruni
IPC分类号： G06F1/3203 , H01L23/367 , H01L23/538 , H02M3/10
CPC分类号： G06F1/3203 , H01L23/3677 , H01L23/5381 , H01L23/5385 , H01L23/5386 , H02M3/10 , H01L2924/37001
摘要： A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.
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公开(公告)号：US12015402B1
公开(公告)日：2024-06-18
申请号：US17648124
申请日：2022-01-14
发明人： Amrita Mathuriya , Nabil Imam , Ikenna Odinaka , Rafael Rios , Rajeev Kumar Dokania , Sasikanth Manipatruni
CPC分类号： H03K19/0021 , H03K19/23
摘要： Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.
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