-
公开(公告)号：US12029043B1
公开(公告)日：2024-07-02
申请号：US17552330
申请日：2021-12-15
发明人： Somilkumar J. Rathi , Noriyuki Sato , Niloy Mukherjee , Rajeev Kumar Dokania , Amrita Mathuriya , Tanay Gosavi , Pratyush Pandey , Jason Y. Wu , Sasikanth Manipatruni
IPC分类号： H10B53/30
CPC分类号： H10B53/30
摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.
-
公开(公告)号：US11955512B1
公开(公告)日：2024-04-09
申请号：US17552266
申请日：2021-12-15
发明人： Somilkumar J. Rathi , Noriyuki Sato , Niloy Mukherjee , Rajeev Kumar Dokania , Amrita Mathuriya , Tanay Gosavi , Pratyush Pandey , Jason Y. Wu , Sasikanth Manipatruni
IPC分类号： H01L21/321 , H01L21/768 , H01L49/02
CPC分类号： H01L28/91 , H01L21/3212 , H01L21/76843 , H01L28/92
摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.
-
3.发明公开公开(公告)号：US20230246062A1
公开(公告)日：2023-08-03
申请号：US17649534
申请日：2022-01-31
发明人： Niloy Mukherjee , Somilkumar J. Rathi , Jason Y. Wu , Pratyush Pandey , Zeying Ren , FNU Atiquzzaman , Gabriel Antonio Paulius Velarde , Noriyuki Sato , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Amrita Mathuriya , Ramamoorthy Ramesh , Sasikanth Manipatruni
IPC分类号： H01L49/02 , H01L21/324 , H01L21/768 , H01L27/11507 , H01L45/00
CPC分类号： H01L28/57 , H01L21/324 , H01L21/76832 , H01L27/11507 , H01L28/65 , H01L28/75 , H01L45/147
摘要： A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.
-
公开(公告)号：US11521667B1
公开(公告)日：2022-12-06
申请号：US17359325
申请日：2021-06-25
发明人： Rajeev Kumar Dokania , Noriyuki Sato , Tanay Gosavi , Pratyush Pandey , Debo Olaosebikan , Amrita Mathuriya , Sasikanth Manipatruni
IPC分类号： G11C11/22 , G11C11/417
摘要： A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.
-
公开(公告)号：US11996438B1
公开(公告)日：2024-05-28
申请号：US17552345
申请日：2021-12-15
发明人： Somilkumar J. Rathi , Noriyuki Sato , Niloy Mukherjee , Rajeev Kumar Dokania , Amrita Mathuriya , Tanay Gosavi , Pratyush Pandey , Jason Y. Wu , Sasikanth Manipatruni
摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.
-
6.发明公开公开(公告)号：US20230298905A1
公开(公告)日：2023-09-21
申请号：US17649673
申请日：2022-02-01
发明人： Niloy Mukherjee , Somilkumar J. Rathi , Jason Y. Wu , Pratyush Pandey , Zeying Ren , FNU Atiquzzaman , Gabriel Antonio Paulius Velarde , Noriyuki Sato , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Amrita Mathuriya , Ramamoorthy Ramesh , Sasikanth Manipatruni
IPC分类号： H01L21/324 , H01L21/768 , H01L27/11507 , H01L49/02 , H01L45/00
CPC分类号： H01L21/324 , H01L21/76832 , H01L27/11507 , H01L28/57 , H01L28/65 , H01L28/75 , H01L45/147
摘要： A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.
-
公开(公告)号：US11527278B1
公开(公告)日：2022-12-13
申请号：US17367101
申请日：2021-07-02
发明人： Rajeev Kumar Dokania , Noriyuki Sato , Tanay Gosavi , Pratyush Pandey , Debo Olaosebikan , Amrita Mathuriya , Sasikanth Manipatruni
IPC分类号： G11C11/22 , G11C11/417
摘要： A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.
-
公开(公告)号：US11527277B1
公开(公告)日：2022-12-13
申请号：US17339850
申请日：2021-06-04
发明人： Rajeev Kumar Dokania , Noriyuki Sato , Tanay Gosavi , Pratyush Pandey , Debo Olaosebikan , Amrita Mathuriya , Sasikanth Manipatruni
IPC分类号： G11C11/22 , G11C11/417
摘要： A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.
-
9.发明授权公开(公告)号：US12022662B1
公开(公告)日：2024-06-25
申请号：US17552321
申请日：2021-12-15
发明人： Somilkumar J. Rathi , Noriyuki Sato , Niloy Mukherjee , Rajeev Kumar Dokania , Amrita Mathuriya , Tanay Gosavi , Pratyush Pandey , Jason Y. Wu , Sasikanth Manipatruni
IPC分类号： H10B53/30
CPC分类号： H10B53/30
摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.
-
公开(公告)号：US12016185B1
公开(公告)日：2024-06-18
申请号：US17552293
申请日：2021-12-15
发明人： Somilkumar J. Rathi , Noriyuki Sato , Niloy Mukherjee , Rajeev Kumar Dokania , Amrita Mathuriya , Tanay Gosavi , Pratyush Pandey , Jason Y. Wu , Sasikanth Manipatruni
IPC分类号： H10B53/30
CPC分类号： H10B53/30
摘要： A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.
-
-
-
-
-
-
-
-
-
搜索结果
29 条记录 (耗时 0.016 秒)
