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公开(公告)号：US20240047426A1
公开(公告)日：2024-02-08
申请号：US18358552
申请日：2023-07-25
IPC分类号： H01L25/065 , H01L23/525 , G06F9/50 , H01L23/00 , G11C7/10 , G11C11/419 , H10B10/00
CPC分类号： H01L25/0657 , H01L23/525 , G06F9/5077 , H01L24/73 , G11C7/1006 , G11C11/419 , H10B10/00 , H01L2224/32145
摘要： Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.
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公开(公告)号：US11894417B2
公开(公告)日：2024-02-06
申请号：US17649899
申请日：2022-02-03
发明人： Niloy Mukherjee , Somilkumar J. Rathi , Jason Y. Wu , Pratyush Pandey , Zeying Ren , FNU Atiquzzaman , Gabriel Antonio Paulius Velarde , Noriyuki Sato , Mauricio Manfrini , Tanay Gosavi , Rajeev Kumar Dokania , Amrita Mathuriya , Ramamoorthy Ramesh , Sasikanth Manipatruni
IPC分类号： H01L21/768 , H01L21/324 , H10B53/30 , H10N70/20 , H10N70/00 , H01L23/522 , H01L49/02
CPC分类号： H01L28/57 , H01L21/324 , H01L21/76832 , H01L28/65 , H01L28/75 , H10B53/30 , H10N70/8836
摘要： A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.
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3.发明授权公开(公告)号：US11832451B1
公开(公告)日：2023-11-28
申请号：US17396609
申请日：2021-08-06
发明人： Debraj Guhabiswas , Maria Isabel Perez , Jason Y. Wu , James David Clarkson , Gabriel Antonio Paulius Velarde , Niloy Mukherjee , Noriyuki Sato , Amrita Mathuriya , Sasikanth Manipatruni , Ramamoorthy Ramesh
摘要： Non lead-based perovskite ferroelectric devices for high density memory and logic applications and methods of fabrication are described. While various embodiments are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For example, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.
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公开(公告)号：US20230308102A1
公开(公告)日：2023-09-28
申请号：US18320163
申请日：2023-05-18
发明人： Sasikanth Manipatruni , Yuan-Sheng Fang , Robert Menezes , Rajeev Kumar Dokania , Guarav Thareja , Ramamoorthy Ramesh , Amrita Mathuriya
摘要： An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.
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公开(公告)号：US11744081B1
公开(公告)日：2023-08-29
申请号：US17315139
申请日：2021-05-07
发明人： Niloy Mukherjee , Ramamoorthy Ramesh , Sasikanth Manipatruni , James Clarkson , FNU Atiquzzaman , Gabriel Antonio Paulius Velarde , Jason Y. Wu
摘要： Described are ferroelectric device film stacks which include a templating or texturing layer or material deposited below a ferroelectric layer, to enable a crystal lattice of the subsequently deposited ferroelectric layer to template off this templating layer and provide a large degree of preferential orientation despite the lack of epitaxial substrates.
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公开(公告)号：US11711083B2
公开(公告)日：2023-07-25
申请号：US17654055
申请日：2022-03-08
发明人： Sasikanth Manipatruni , Yuan-Sheng Fang , Robert Menezes , Rajeev Kumar Dokania , Guarav Thareja , Ramamoorthy Ramesh , Amrita Mathuriya
摘要： An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.
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公开(公告)号：US11637090B2
公开(公告)日：2023-04-25
申请号：US17390829
申请日：2021-07-30
IPC分类号： H01L25/065 , H01L23/525 , H01L23/00 , G06F9/50 , G11C7/10 , G11C11/419 , H01L27/11
摘要： Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.
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公开(公告)号：US20230116124A1
公开(公告)日：2023-04-13
申请号：US18048019
申请日：2022-10-19
摘要： Described is a low power, high-density non-volatile differential memory bit-cell. The transistors of the differential memory bit-cell can be planar or non-planer and can be fabricated in the frontend or backend of a die. A bit-cell of the non-volatile differential memory bit-cell comprises first transistor first non-volatile structure that are controlled to store data of a first value. Another bit-cell of the non-volatile differential memory bit-cell comprises second transistor and second non-volatile structure that are controlled to store data of a second value, wherein the first value is an inverse of the second value. The first and second volatile structures comprise ferroelectric material (e.g., perovskite, hexagonal ferroelectric, improper ferroelectric).
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公开(公告)号：US11616507B2
公开(公告)日：2023-03-28
申请号：US17390831
申请日：2021-07-30
发明人： Sasikanth Manipatruni , Yuan-Sheng Fang , Robert Menezes , Rajeev Kumar Dokania , Ramamoorthy Ramesh , Amrita Mathuriya
摘要： A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.
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公开(公告)号：US11482529B2
公开(公告)日：2022-10-25
申请号：US16288004
申请日：2019-02-27
IPC分类号： H01L27/11507 , H01L49/02 , G11C11/22 , H01L27/11514 , H01L21/02 , G11C11/402 , H01L27/108 , H01L29/78
摘要： Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.
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