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1.发明公开公开(公告)号：US20240345805A1
公开(公告)日：2024-10-17
申请号：US18753107
申请日：2024-06-25
发明人： Pankaj GUPTA , Karthik SUBBURAJ , Sujaata RAMALINGAM , Karthik RAMASUBRAMANIAN , Indu PRATHAPAN
CPC分类号： G06F7/49 , G06F7/501 , G06F17/142
摘要： A system includes Radix-22 butterfly stages, each including first and second Radix-22 butterfly circuits, in which the first Radix-22 butterfly circuit of a first Radix-22 butterfly stage includes a data input coupled to a system data input, and one of the first Radix-22 butterfly circuit and the second Radix-22 butterfly circuit of a last Radix-22 butterfly stage includes a data output coupled to a system data output. The system further includes a Radix-3 butterfly circuit including a data input coupled to the system data input and a data output selectively couplable to a data input of one of the first or second Radix-22 butterfly circuits of a second or later Radix-22 butterfly stage based on a particular point transform to be performed by the system. A set of memories are used by either the first Radix-22 butterfly stage or the Radix-3 butterfly circuit, depending on the particular point transform.
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公开(公告)号：US12106822B2
公开(公告)日：2024-10-01
申请号：US17852193
申请日：2022-06-28
发明人： Chetan Deshpande , Gajanan Sahebrao Jedhe , Gaurang Prabhakar Narvekar , Cheng-Xin Xue , Sushil Kumar , Zijie Guo
CPC分类号： G11C7/1069 , G06F7/501 , G06F7/5443 , G11C7/1012 , G11C7/1096 , G11C7/12 , G11C8/06 , G11C8/08
摘要： Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a memory array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, an activation architecture is provided using a bit cell array arranged in rows and columns to store charges that represent a weight value in a weight matrix. A read word line (RWL) may be repurposed to provide the input activation value to bit cells within a row of bit cells, while a read-bit line (RBL) is configured to receive multiplication products from bit cells arranged in a column. Some embodiments provide multiple sub-arrays or tiles of bit cell arrays.
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3.发明授权公开(公告)号：US12075179B2
公开(公告)日：2024-08-27
申请号：US18047588
申请日：2022-10-18
发明人： Rui Wang
IPC分类号： H04N25/772 , G06F7/501 , G06F7/57
CPC分类号： H04N25/772 , G06F7/501 , G06F7/57
摘要： An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. An adder input latch stage includes first and second adder input latches including first and second inputs coupled to receive outputs of the GC to binary stage. An adder input multiplexer stage includes an output coupled to second inputs of the adder stage, and first and second inputs coupled to outputs the first and second adder input latches, respectively.
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4.发明授权公开(公告)号：US12045582B2
公开(公告)日：2024-07-23
申请号：US17351699
申请日：2021-06-18
发明人： Pankaj Gupta , Karthik Subburaj , Sujaata Ramalingam , Karthik Ramasubramanian , Indu Prathapan
CPC分类号： G06F7/49 , G06F7/501 , G06F17/142
摘要： A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.
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公开(公告)号：US20240126507A1
公开(公告)日：2024-04-18
申请号：US18544313
申请日：2023-12-18
摘要： Adder circuits and associated methods for processing a set of at least three floating-point numbers to be added together include identifying, from among the at least three numbers, at least two numbers that have the same sign—that is, at least two numbers that are both positive or both negative. The identified at least two numbers are added together using one or more same-sign floating-point adders. A same-sign floating-point adder comprises circuitry configured to add together floating-point numbers having the same sign and does not include circuitry configured to add together numbers having different signs.
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公开(公告)号：US20240112003A1
公开(公告)日：2024-04-04
申请号：US18077993
申请日：2022-12-08
发明人： HIEU VAN TRAN , STEPHEN TRINH , STANLEY HONG , THUAN VU , NGHIA LE , HIEN PHAM
摘要： Numerous examples are disclosed of output circuitry and associated methods in an artificial neural network. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period, a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period, and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.
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公开(公告)号：US20240094987A1
公开(公告)日：2024-03-21
申请号：US18329856
申请日：2023-06-06
发明人： Byoung Gon Kang
IPC分类号： G06F7/501 , G06F30/392 , H01L27/118 , H03K17/00 , H03K19/21
CPC分类号： G06F7/501 , G06F30/392 , H01L27/11807 , H03K17/002 , H03K19/21 , H01L2027/11881 , H01L2027/11885
摘要： A compressor circuit and a semiconductor integrated circuit included the compressor circuit are provided. The semiconductor integrated circuit includes a compressor circuit which includes a first full adder circuit which receives an A1 signal, a B1 signal, and a CI signal to output an IS signal and an ICO signal, and a second full adder circuit which receives a B2 signal, the IS signal, and a CI2 signal to output an S signal and a CO signal. Each of the first full adder circuit and the second full adder circuit are in an L-shaped layout, the first full adder circuit and the second full adder circuit have bent portions that are point-symmetrically engaged with each other, and the compressor circuit is in a rectangular shape. The number of transistors in the second full adder circuit is smaller than the number of transistors in the first full adder circuit.
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公开(公告)号：US11894863B2
公开(公告)日：2024-02-06
申请号：US17884935
申请日：2022-08-10
发明人： Myung Hoon Sunwoo , U Seok Lee
CPC分类号： H03M13/6572 , H03M13/1108 , G06F7/501
摘要： Disclosed are a method and apparatus for generating a decoding position control signal for decoding using polar codes. The method and apparatus for generating a decoding position control signal for decoding using polar codes according to an embodiment of the present disclosure include generating a decoding tree obtained by forming a plurality of nodes in a hierarchical structure for a polar-encoded codeword, decoding the codeword using a successive cancellation (SC) decoding technique, and generating control signal through a preset operation relationship based on a position of a bit returned during re-decoding among the decoded codeword.
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公开(公告)号：US11783875B2
公开(公告)日：2023-10-10
申请号：US17828964
申请日：2022-05-31
发明人： Mingoo Seok , Zhewei Jiang , Jae-sun Seo , Shihui Yin
CPC分类号： G11C7/1036 , G06F7/501 , G06F7/5443 , G11C7/1051 , G11C7/1078 , G11C15/04 , G11C15/043 , G11C16/3404
摘要： In some embodiments, an in-memory-computing SRAM macro based on capacitive-coupling computing (C3) (which is referred to herein as “C3SRAM”) is provided. In some embodiments, a C3SRAM macro can support array-level fully parallel computation, multi-bit outputs, and configurable multi-bit inputs. The macro can include circuits embedded in bitcells and peripherals to perform hardware acceleration for neural networks with binarized weights and activations in some embodiments. In some embodiments, the macro utilizes analog-mixed-signal capacitive-coupling computing to evaluate the main computations of binary neural networks, binary-multiply-and-accumulate operations. Without needing to access the stored weights by individual row, the macro can assert all of its rows simultaneously and form an analog voltage at the read bitline node through capacitive voltage division, in some embodiments. With one analog-to-digital converter (ADC) per column, the macro cab realize fully parallel vector-matrix multiplication in a single cycle in accordance with some embodiments.
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公开(公告)号：US20230308102A1
公开(公告)日：2023-09-28
申请号：US18320163
申请日：2023-05-18
发明人： Sasikanth Manipatruni , Yuan-Sheng Fang , Robert Menezes , Rajeev Kumar Dokania , Guarav Thareja , Ramamoorthy Ramesh , Amrita Mathuriya
摘要： An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.
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