-
公开(公告)号：US12112410B2
公开(公告)日：2024-10-08
申请号：US17752458
申请日：2022-05-24
发明人： Casper Van Benthem
CPC分类号： G06T11/40 , G06T1/20 , G06T7/13 , G06T15/005 , G06T15/503 , G06T15/80 , G09G5/363 , G06T2207/20021 , G06T2210/12 , G09G2360/122 , G06T15/005 , G06T11/40 , G06T1/20 , G06T15/80 , G06T7/13 , G06T15/503 , G06T2207/20021 , G06T2210/12 , G09G5/363 , G09G2360/122
摘要： Conservative rasterization hardware comprises hardware logic arranged to perform an edge test calculation for each edge of a primitive and for two corners of each pixel in a microtile. The two corners that are used are selected based on the gradient of the edge and the edge test result for one corner is the inner coverage result and the edge test result for the other corner is the outer coverage result for the pixel. An overall outer coverage result for the pixel and the primitive is calculated by combining the outer coverage results for the pixel and each of the edges of the primitive in an AND gate. The overall inner coverage result for the pixel is calculated in a similar manner.
-
公开(公告)号：US11741654B2
公开(公告)日：2023-08-29
申请号：US17557227
申请日：2021-12-21
发明人： Casper Van Benthem
CPC分类号： G06T15/005 , G06T17/20 , G06T2210/36
摘要： A graphics processing hardware pipeline is arranged to perform an edge test or a depth calculation. Each hardware arrangement includes a microtile component hardware element, multiple pixel component hardware elements, one or more subsample component hardware elements and a final addition and comparison unit. The microtile component hardware element calculates a first output using a sum-of-products and coordinates of a microtile within a tile in the rendering space. Each pixel component hardware element calculates a different second output using the sum-of-products and coordinates for different pixels defined relative to an origin of the microtile. The subsample component hardware element calculates a third output using the sum-of-products and coordinates for a subsample position defined relative to an origin of a pixel. The adders sum different combinations of the first output, a second output and a third output to generate output results for different subsample positions defined relative to the origin of the tile.
-
公开(公告)号：US20220156043A1
公开(公告)日：2022-05-19
申请号：US17588671
申请日：2022-01-31
摘要： Adder circuits and associated methods for processing a set of at least three floating-point numbers to be added together include identifying, from among the at least three numbers, at least two numbers that have the same sign—that is, at least two numbers that are both positive or both negative. The identified at least two numbers are added together using one or more same-sign floating-point adders. A same-sign floating-point adder comprises circuitry configured to add together floating-point numbers having the same sign and does not include circuitry configured to add together numbers having different signs.
-
公开(公告)号：US20220114779A1
公开(公告)日：2022-04-14
申请号：US17557227
申请日：2021-12-21
发明人： Casper Van Benthem
摘要： A graphics processing hardware pipeline is arranged to perform an edge test or a depth calculation. Each hardware arrangement includes a microtile component hardware element, multiple pixel component hardware elements, one or more subsample component hardware elements and a final addition and comparison unit. The microtile component hardware element calculates a first output using a sum-of-products and coordinates of a microtile within a tile in the rendering space. Each pixel component hardware element calculates a different second output using the sum-of-products and coordinates for different pixels defined relative to an origin of the microtile. The subsample component hardware element calculates a third output using the sum-of-products and coordinates for a subsample position defined relative to an origin of a pixel. The adders sum different combinations of the first output, a second output and a third output to generate output results for different subsample positions defined relative to the origin of the tile.
-
5.发明授权公开(公告)号：US11294625B2
公开(公告)日：2022-04-05
申请号：US15293541
申请日：2016-10-14
发明人： Casper Van Benthem , Sam Elliott
摘要： Methods and systems for determining whether an infinitely precise result of a reciprocal square root operation performed on an input floating point number is greater than a particular number in a first floating point precision. The method includes calculating the square of the particular number in a second lower floating point precision; calculating an error in the calculated square due to the second floating point precision; calculating a first delta value in the first floating point precision by calculating the square multiplied by the input floating point number less one; calculating a second delta value by calculating the error multiplied by the input floating point number plus the first delta value; and outputting an indication of whether the infinitely precise result of the reciprocal square root operation is greater than the particular number based on the second delta term.
-
公开(公告)号：US20190311516A1
公开(公告)日：2019-10-10
申请号：US15981102
申请日：2018-05-16
发明人： Casper Van Benthem
摘要： A graphics processing hardware pipeline is arranged to perform an edge test or a depth calculation. Each hardware arrangement includes a microtile component hardware element, multiple pixel component hardware elements, one or more subsample component hardware elements and a final addition and comparison unit. The microtile component hardware element calculates a first output using a sum-of-products and coordinates of a microtile within a tile in the rendering space. Each pixel component hardware element calculates a different second output using the sum-of-products and coordinates for different pixels defined relative to an origin of the microtile. The subsample component hardware element calculates a third output using the sum-of-products and coordinates for a subsample position defined relative to an origin of a pixel. The adders sum different combinations of the first output, a second output and a third output to generate output results for different subsample positions defined relative to the origin of the tile.
-
公开(公告)号：US20230401779A1
公开(公告)日：2023-12-14
申请号：US18239224
申请日：2023-08-29
发明人： Casper Van Benthem
CPC分类号： G06T15/005 , G06T17/20 , G06T2210/36
摘要： A graphics processing hardware pipeline is arranged to perform an edge test or a depth calculation. Each hardware arrangement includes a microtile component hardware element, multiple pixel component hardware elements, one or more subsample component hardware elements and a final addition and comparison unit. The microtile component hardware element calculates a first output using a sum-of-products and coordinates of a microtile within a tile in the rendering space. Each pixel component hardware element calculates a different second output using the sum-of-products and coordinates for different pixels defined relative to an origin of the microtile. The subsample component hardware element calculates a third output using the sum-of-products and coordinates for a subsample position defined relative to an origin of a pixel. The adders sum different combinations of the first output, a second output and a third output to generate output results for different subsample positions defined relative to the origin of the tile.
-
公开(公告)号：US11768658B2
公开(公告)日：2023-09-26
申请号：US17875747
申请日：2022-07-28
发明人： Casper Van Benthem
CPC分类号： G06F5/01 , G06F7/49936
摘要： Apparatus includes hardware logic arranged to normalise an n-bit input number. The hardware logic comprises at least a first hardware logic stage, an intermediate hardware logic stage and a final hardware logic stage. Each stage comprises a left shifting logic element, the first and intermediate stages each also comprise a plurality of OR-reduction logic elements and the intermediate and final stages each also comprise one or more multiplexers. The OR-reduction logic elements operate on different subsets of bits from the number input to the particular stage. In the intermediate and final hardware logic stages, a first of the multiplexers selects an OR-reduction result received from a previous hardware logic stage and the left shifting logic element is arranged to perform left shifting on the updated binary number received from an immediately previous hardware logic stage dependent upon the selected OR-reduction result.
-
公开(公告)号：US11710263B2
公开(公告)日：2023-07-25
申请号：US17744649
申请日：2022-05-14
发明人： Casper Van Benthem
CPC分类号： G06T11/203 , G06T1/20
摘要： A method of rasterising a line in computer graphics determines whether the line's start and/or end is inside a diamond test area within the pixel. If the end is not inside and the start is inside, the pixel is drawn as part of the line. If neither the start nor the end of the line are inside, it is determined whether the line crosses more than one extended diamond edge and if so, it is further determined (i) whether an extended line passing through the start and end is substantially vertical and touches the right point of the diamond area, (ii) if the extended line touches the bottom point of the diamond area, and (iii) whether the extended line is on a same side of each point of the diamond area. If any of (i), (ii) and (iii) is positive, the pixel is drawn as part of the line.
-
公开(公告)号：US20220270307A1
公开(公告)日：2022-08-25
申请号：US17744649
申请日：2022-05-14
发明人： Casper Van Benthem
摘要： A method of rasterising a line in computer graphics determines whether the line's start and/or end is inside a diamond test area within the pixel. If the end is not inside and the start is inside, the pixel is drawn as part of the line. If neither the start nor the end of the line are inside, it is determined whether the line crosses more than one extended diamond edge and if so, it is further determined (i) whether an extended line passing through the start and end is substantially vertical and touches the right point of the diamond area, (ii) if the extended line touches the bottom point of the diamond area, and (iii) whether the extended line is on a same side of each point of the diamond area. If any of (i), (ii) and (iii) is positive, the pixel is drawn as part of the line.
-
-
-
-
-
-
-
-
-
搜索结果
51 条记录 (耗时 0.027 秒)
