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1.发明公开公开(公告)号：US20240126965A1
公开(公告)日：2024-04-18
申请号：US18216196
申请日：2023-06-29
Applicant: Imagination Technologies Limited
Inventor： Rachel Edmonds , Sam Elliott , Simon Gaulter
CPC classification number: G06F30/33 , G06F7/49915
Abstract: Methods of verifying a property of a hardware design for an integrated circuit to implement a product of power functions of the form x0t0× . . . ×xntn, wherein t0 . . . tn are fixed, rational numbers, x0 . . . xn are floating point inputs, and n is an integer greater than or equal to one. A first verification phase comprises formally verifying that, for any first non-exception input set X=X0, . . . , Xn and any second non-exception input set Y=Y0, . . . , Yn in an input space wherein corresponding inputs have a same mantissa and (t0X0.exp+ . . . +tnXn.exp)−(t0Y0.exp+ . . . +tnYn.exp) is an integer, an instantiation of the hardware design generates outputs X′ and Y′ with a same mantissa and X′exp−(t0X0.exp+ . . . +tnXn.exp)=Y′exp−(t0Y0.exp+ . . . +tnYn.exp); and second verification phase comprises verifying the property for the hardware design for a subset of input sets in the input space, the subset of input sets selected based on exponents sets wherein (t0X0.exp+ . . . +tnXn.exp)−(t0Y0.exp+ . . . +tnYn.exp) is an integer.
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公开(公告)号：US11475193B2
公开(公告)日：2022-10-18
申请号：US17167698
申请日：2021-02-04
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Sam Elliott
IPC: G06F30/3312 , G06F119/12 , G06F30/33
Abstract: Methods and systems for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. The method includes: (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process; (b) in response to determining the watched data has been input to the pipelined process counting a number of progressing clock cycles for the watched data; and (c) evaluating an assertion written in an assertion based language, the assertion establishing that when the watched data is output from the pipelined process the counted number of progressing clock cycles for the watched data should be equal to one of one or more predetermined values.
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公开(公告)号：US20220156043A1
公开(公告)日：2022-05-19
申请号：US17588671
申请日：2022-01-31
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott , Jonas Olof Gunnar KALLEN , Casper Van Benthem
Abstract: Adder circuits and associated methods for processing a set of at least three floating-point numbers to be added together include identifying, from among the at least three numbers, at least two numbers that have the same sign—that is, at least two numbers that are both positive or both negative. The identified at least two numbers are added together using one or more same-sign floating-point adders. A same-sign floating-point adder comprises circuitry configured to add together floating-point numbers having the same sign and does not include circuitry configured to add together numbers having different signs.
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4.发明授权公开(公告)号：US11294625B2
公开(公告)日：2022-04-05
申请号：US15293541
申请日：2016-10-14
Applicant: Imagination Technologies Limited
Inventor： Casper Van Benthem , Sam Elliott
Abstract: Methods and systems for determining whether an infinitely precise result of a reciprocal square root operation performed on an input floating point number is greater than a particular number in a first floating point precision. The method includes calculating the square of the particular number in a second lower floating point precision; calculating an error in the calculated square due to the second floating point precision; calculating a first delta value in the first floating point precision by calculating the square multiplied by the input floating point number less one; calculating a second delta value by calculating the error multiplied by the input floating point number plus the first delta value; and outputting an indication of whether the infinitely precise result of the reciprocal square root operation is greater than the particular number based on the second delta term.
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公开(公告)号：US20210294949A1
公开(公告)日：2021-09-23
申请号：US17207030
申请日：2021-03-19
Applicant: Imagination Technologies Limited
Inventor： Simon Gaulter , Thomas Ferrere , Faizan Nazar , Sam Elliott
IPC: G06F30/33
Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.
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Patent Agency Ranking
公开(公告)号：US11106847B2
公开(公告)日：2021-08-31
申请号：US16848934
申请日：2020-04-15
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott , Robert McKemey , Max Freiburghaus
IPC: G06F30/3323 , G06F119/16
Abstract: Methods and systems for verifying a hardware design for an integrated circuit that implements a function that is polynomial in an input variable x over a set of values of x. The method includes formally verifying that a first instantiation of the hardware design implements a function that is polynomial of degree k in x by formally verifying that for all x in the set of values of x the first instantiation of the hardware design has a constant kth difference; and verifying that a second instantiation of the hardware design generates an expected output in response to each of at least k different values of x in the set of values of x.
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公开(公告)号：US11074381B2
公开(公告)日：2021-07-27
申请号：US17065678
申请日：2020-10-08
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott
IPC: G06F30/30 , G06F30/33 , G06F30/337 , G06F30/3323 , G01R31/3183 , G01R31/00 , G06F30/3308 , G06F115/02 , G06F119/16 , G06F111/12
Abstract: A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) a plurality of leaf data transformation components which do not have children, and (ii) one or more parent data transformation components which each comprise one or more child data transformation components. For each of the plurality of leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. For each of the one or more parent data transformation components, it is formally verified, using a formal verification tool, that an instantiation of an abstracted hardware design for the parent data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the one or more child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component is configured to produce a specific output transaction with a causal deterministic relationship to the specific input transaction.
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公开(公告)号：US20210103691A1
公开(公告)日：2021-04-08
申请号：US17065678
申请日：2020-10-08
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott
IPC: G06F30/323 , G06F30/331 , G06F30/337 , G06F9/46
Abstract: A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) a plurality of leaf data transformation components which do not have children, and (ii) one or more parent data transformation components which each comprise one or more child data transformation components. For each of the plurality of leaf data transformation components, it is verified that an instantiation of the hardware design for the leaf data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. For each of the one or more parent data transformation components, it is formally verified, using a formal verification tool, that an instantiation of an abstracted hardware design for the parent data transformation component generates an expected output transaction in response to each of a plurality of test input transactions. The abstracted hardware design for the parent data transformation component represents each of the one or more child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component is configured to produce a specific output transaction with a causal deterministic relationship to the specific input transaction.
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公开(公告)号：US10949590B2
公开(公告)日：2021-03-16
申请号：US16399218
申请日：2019-04-30
Applicant: Imagination Technologies Limited
Inventor： Ashish Darbari , Sam Elliott
IPC: G06F30/3312 , G06F30/33 , G06F119/12
Abstract: Methods and systems for verifying that logic for implementing a pipelined process in hardware correctly moves data through the pipelined process. The method includes: (a) monitoring data input to the pipelined process to determine when watched data has been input to the pipelined process; (b) in response to determining the watched data has been input to the pipelined process counting a number of progressing clock cycles for the watched data; and (c) evaluating an assertion written in an assertion based language, the assertion establishing that when the watched data is output from the pipelined process the counted number of progressing clock cycles for the watched data should be equal to one of one or more predetermined values.
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公开(公告)号：US20240320407A1
公开(公告)日：2024-09-26
申请号：US18675048
申请日：2024-05-27
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott
IPC: G06F30/33 , G01R31/3183 , G06F30/3308 , G06F30/3323 , G06F30/337 , G06F111/12 , G06F115/02 , G06F119/16
CPC classification number: G06F30/33 , G01R31/318314 , G06F30/3323 , G06F30/337 , G06F30/3308 , G06F2111/12 , G06F2115/02 , G06F2119/16
Abstract: A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) leaf data transformation components which do not have children, and (ii) parent data transformation components which comprise one or more child data transformation components. For each of the leaf data transformation components, it is verified that an instantiation of the hardware design generates an expected output transaction. For each of the parent data transformation components, it is formally verified that an instantiation of an abstracted hardware design generates an expected output transaction in response to each of test input transactions. The abstracted hardware design represents each of the child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component produces a specific output transaction with a causal deterministic relationship to the specific input transaction.
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