公开(公告)号：US20240354477A1

公开(公告)日：2024-10-24

申请号：US18137382

申请日：2023-04-20

Applicant: Synopsys, Inc.

Inventor： Navneet KAKKAR ,  Sridhar KELADI

IPC: G06F30/327 ,  G06F30/33

CPC classification number: G06F30/327 ,  G06F30/33

Abstract: Certain aspects are directed to apparatus and methods for logic synthesis. One example method generally includes: receiving a logic design including a representation of a plurality of registers and ports; detecting one or more constant, equal, or opposite registers or ports of the plurality of registers and ports by analyzing logic across a hierarchy boundary identified for the logic synthesis; and generating a netlist by modifying the logic based on the detection.

公开(公告)号：US20240346217A1

公开(公告)日：2024-10-17

申请号：US18299427

申请日：2023-04-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jaw-Juinn Horng ,  Szu-Chin Tsao

IPC: G06F30/33 ,  G06F30/327

CPC classification number: G06F30/33 ,  G06F30/327

Abstract: An integrated circuit includes a core domain having at least one core domain design rule limitation of a smaller device and a lower operating voltage, an input/output domain having at least one input/output domain design rule limitation of a larger device than the smaller device of the core domain and a higher operating voltage than the lower operating voltage of the core domain, and a mapping cell that includes two or more electrical devices that each meet the at least one core domain design rule limitation. The mapping cell is configured to be an input/output device and operate in the input/output domain at the higher operating voltage of the input/output domain.

公开(公告)号：US20240320407A1

公开(公告)日：2024-09-26

申请号：US18675048

申请日：2024-05-27

Applicant: Imagination Technologies Limited

Inventor： Sam Elliott

IPC: G06F30/33 ,  G01R31/3183 ,  G06F30/3308 ,  G06F30/3323 ,  G06F30/337 ,  G06F111/12 ,  G06F115/02 ,  G06F119/16

CPC classification number: G06F30/33 ,  G01R31/318314 ,  G06F30/3323 ,  G06F30/337 ,  G06F30/3308 ,  G06F2111/12 ,  G06F2115/02 ,  G06F2119/16

Abstract: A hardware design for a main data transformation component is verified. The main data transformation component is representable as a hierarchical set of data transformation components which includes (i) leaf data transformation components which do not have children, and (ii) parent data transformation components which comprise one or more child data transformation components. For each of the leaf data transformation components, it is verified that an instantiation of the hardware design generates an expected output transaction. For each of the parent data transformation components, it is formally verified that an instantiation of an abstracted hardware design generates an expected output transaction in response to each of test input transactions. The abstracted hardware design represents each of the child data transformation components of the parent data transformation component with a corresponding abstracted component that for a specific input transaction to the child data transformation component produces a specific output transaction with a causal deterministic relationship to the specific input transaction.

公开(公告)号：US12073158B2

公开(公告)日：2024-08-27

申请号：US17521162

申请日：2021-11-08

Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED

Inventor： Yuqin Chen ,  Changyu Hsieh ,  Shengyu Zhang

IPC: G06F30/33 ,  G06F119/10 ,  G06N10/00

CPC classification number: G06F30/33 ,  G06N10/00 ,  G06F2119/10

Abstract: This application provides a quantum noise process analysis method, system, storage medium, and electronic device, which are applied in the field of quantum information processing technology. The method includes: preparing quantum initial states; respectively inputting the quantum initial states into a plurality of first circuits to obtain a plurality of first quantum output states; determining a first dynamical map eigenspectrum according to a functional correspondence between the plurality of first quantum output states and the quantum initial states; respectively inputting the quantum initial states into a plurality of second circuits to obtain a plurality of second quantum output states; determining a second dynamical map eigenspectrum according to a functional correspondence between the plurality of second quantum output states and the quantum initial states; and determining a dynamical map eigenspectrum of a quantum noise process according to the first dynamical map eigenspectrum and the second dynamical map eigenspectrum.

公开(公告)号：US12045550B2

公开(公告)日：2024-07-23

申请号：US18297350

申请日：2023-04-07

Applicant: Aurora Labs Ltd.

Inventor： Zohar Fox ,  Carmit Sahar

IPC: G06F8/75 ,  G06F8/34 ,  G06F8/65 ,  G06F8/71 ,  G06F11/36 ,  G06F16/901 ,  G06F17/18 ,  G06F18/24 ,  G06F21/52 ,  G06F21/56 ,  G06F21/57 ,  G06F21/62 ,  G06F30/33 ,  G06N20/00 ,  G06F30/15 ,  G10H1/00

CPC classification number: G06F30/33 ,  G06F8/34 ,  G06F8/65 ,  G06F8/71 ,  G06F8/75 ,  G06F11/3604 ,  G06F11/3612 ,  G06F11/362 ,  G06F11/3692 ,  G06F16/9014 ,  G06F17/18 ,  G06F18/24 ,  G06F21/52 ,  G06F21/563 ,  G06F21/57 ,  G06F21/6218 ,  G06N20/00 ,  G06F30/15 ,  G10H1/0058

Abstract: Disclosed herein are techniques for analyzing software delta changes based on functional line-of-code behavior and relation models. Techniques include identifying a prompt to change a first version of code on a controller to a second version of code; constructing, based on the identified prompt, a line-of-code behavior and relation model representing execution of functions of the controller based on the second version of code; performing a signature operation on the generated line-of-code behavior and relation model to produce a signature value; and sending the signature value to the controller; wherein the controller is configured to compare the signature value to a computed signature value that the controller is configured to compute based on the second version of code and determine, based on the comparison, whether to validate the second version of code.

公开(公告)号：US12026083B2

公开(公告)日：2024-07-02

申请号：US16908322

申请日：2020-06-22

Applicant: WAPP TECH CORP.

Inventor： Donavan Paul Poulin

IPC: G06F9/455 ,  G06F8/30 ,  G06F8/71 ,  G06F11/34 ,  G06F11/36 ,  G06F30/33

CPC classification number: G06F11/3664 ,  G06F8/30 ,  G06F8/71 ,  G06F11/3457 ,  G06F11/3668 ,  G06F30/33 ,  G06F9/455 ,  G06F2201/00 ,  G06F2201/86

Abstract: A system, method and software product emulate and profile an application playing on a mobile device. The mobile device is emulated using a model based upon characteristics related to performance of the mobile device. The application is played and monitored within the model to determine resource utilization of the application for the mobile device.

公开(公告)号：US20240160818A1

公开(公告)日：2024-05-16

申请号：US17985735

申请日：2022-11-11

Applicant: XILINX, INC.

Inventor： Federico VENINI ,  David TRAN

IPC: G06F30/33 ,  G06F30/323

CPC classification number: G06F30/33 ,  G06F30/323 ,  G06F2119/02

Abstract: Safety mechanisms are embedded into a System on a Chip (SoC) and are operable to detect faults present in the logic circuitry in the SoC. Various types of faults in logic circuitry can occur, for example, a bit stuck at 0 or 1, or a transient or temporary fault due to radiation impacting the SoC. SoC devices are required to meet certain automotive safety integrity standards. The most stringent automotive safety integrity level requires that 90% of random latent faults are detected in all relevant logic, including all safety mechanism. Examples disclosed include hardware based checkers and hardware or software based pattern generation methods that achieve high online fault coverage in safety mechanism circuitry used for functional safety. A hardware based safety mechanism monitors the logic circuitry during operation. Any time the safety mechanism detects any faults in the logic circuitry, a fault notification is propagated to upstream logic.

公开(公告)号：US11960807B2

公开(公告)日：2024-04-16

申请号：US17929792

申请日：2022-09-06

Applicant: Aurora Labs Ltd.

Inventor： Zohar Fox ,  Carmit Sahar

IPC: G06F30/33 ,  G06F8/34 ,  G06F8/65 ,  G06F8/71 ,  G06F8/75 ,  G06F11/36 ,  G06F16/901 ,  G06F17/18 ,  G06F18/24 ,  G06F21/52 ,  G06F21/56 ,  G06F21/57 ,  G06F21/62 ,  G06N20/00 ,  G06F30/15 ,  G10H1/00

CPC classification number: G06F30/33 ,  G06F8/34 ,  G06F8/65 ,  G06F8/71 ,  G06F8/75 ,  G06F11/3604 ,  G06F11/3612 ,  G06F11/362 ,  G06F11/3692 ,  G06F16/9014 ,  G06F17/18 ,  G06F18/24 ,  G06F21/52 ,  G06F21/563 ,  G06F21/57 ,  G06F21/6218 ,  G06N20/00 ,  G06F30/15 ,  G10H1/0058

Abstract: Disclosed herein are techniques for using a line-of-code behavior and relation model to determine software functionality changes. Techniques include identifying a first portion of executable code and a second portion of executable code; accessing a first line-of-code behavior and relation model representing execution of functions of the first portion of executable code; constructing, based on the second portion of executable code, a second line-of-code behavior and relation model representing execution of functions of the second portion of executable code; performing a functional differential comparison of the first line-of-code behavior and relation model to the second line-of-code behavior and relation model; determining, based on the functional differential comparison, a status of functional equivalence between the first portion of executable code and the code portion of executable code; and generating, based on the determined difference, a report identifying the status of functional equivalence.

公开(公告)号：US20240104916A1

公开(公告)日：2024-03-28

申请号：US18519674

申请日：2023-11-27

Applicant: Intel Corporation

Inventor： Haim Barad ,  Barak Hurwitz ,  Uzi Sarel ,  Eran Geva ,  Eli Kfir ,  Moshe Island

IPC: G06V10/82 ,  G06F30/33 ,  G06N3/04 ,  G06V10/44 ,  G06V10/94

CPC classification number: G06V10/82 ,  G06F30/33 ,  G06N3/04 ,  G06V10/454 ,  G06V10/955

Abstract: Systems, apparatuses and methods may provide for technology that processes an inference workload in a first subset of layers of a neural network that prevents or inhibits data dependent branch operations, conducts an exit determination as to whether an output of the first subset of layers satisfies one or more exit criteria, and selectively bypasses processing of the output in a second subset of layers of the neural network based on the exit determination. The technology may also speculatively initiate the processing of the output in the second subset of layers while the exit determination is pending. Additionally, when the inference workloads include a plurality of batches, the technology may mask one or more of the plurality of batches from processing in the second subset of layers.

公开(公告)号：US20230385498A1

公开(公告)日：2023-11-30

申请号：US18303219

申请日：2023-04-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sandeep Kumar Goel ,  Ankita Patidar

IPC: G06F30/333 ,  G06F30/33 ,  G06F30/39 ,  G06F30/392

CPC classification number: G06F30/333 ,  G06F30/392 ,  G06F30/39 ,  G06F30/33

Abstract: Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.