-
公开(公告)号：US20250020719A1
公开(公告)日：2025-01-16
申请号：US18350509
申请日：2023-07-11
Inventor： Mohammed Moiz Khan , Sandeep Kumar Goel
IPC: G01R31/3185 , G01R31/3177
Abstract: A circuit includes a scan chain comprising a cell structure, wherein the cell structure comprises a first plural number (N) of stages, and each of the stages is configured to store a bit. The circuit includes a second plural number (S) of multiplexers operatively coupled to the scan chain, wherein the S is determined as N M , where the M represents a diagnostic resolution. The multiplexers are each configured to receive a respective one of S control signals to selectively bypass a corresponding subset of the stages.
-
公开(公告)号：US20240361385A1
公开(公告)日：2024-10-31
申请号：US18767186
申请日：2024-07-09
Inventor： Anshuman Chandra , Sandeep Kumar Goel
IPC: G01R31/3185 , G01R31/3187
CPC classification number: G01R31/318572 , G01R31/318536 , G01R31/318547 , G01R31/318555 , G01R31/3187
Abstract: Systems, methods, and devices are described herein for performing intra-die and inter-die tests of one or more dies of an integrated circuit. A cell of an integrated circuit includes a data register, an I/O pad, and a first multiplexer. The data register is configured to output a signal. The I/O pad is coupled to the data register and configured to receive and buffer the signal. The first multiplexer is coupled to the I/O pad and the data register. The multiplexer is configured to selectively output either the buffered signal or the signal based on whether a scan mode or a functional mode is enabled.
-
公开(公告)号：US11727177B2
公开(公告)日：2023-08-15
申请号：US17836954
申请日：2022-06-09
Inventor： Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
IPC: G06F30/327 , G06F30/398 , G06F30/333 , G06F30/3308 , G06F119/18 , G06F119/02
CPC classification number: G06F30/327 , G06F30/398 , G06F30/333 , G06F30/3308 , G06F2119/02 , G06F2119/18
Abstract: A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a unique dominant feature among a plurality of features of the plurality of paths. The dominant feature of a group among the plurality of groups is slack. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.
-
公开(公告)号：US11699010B2
公开(公告)日：2023-07-11
申请号：US17365468
申请日：2021-07-01
Inventor： Sandeep Kumar Goel , Ankita Patidar , Yun-Han Lee
IPC: G06F30/323 , G06F30/3323 , G06F30/392 , G06F30/394 , G03F1/70 , G06F119/12
CPC classification number: G06F30/323 , G03F1/70 , G06F30/3323 , G06F30/392 , G06F30/394 , G06F2119/12
Abstract: A method of manufacturing a semiconductor device includes reducing errors in a migration of a first netlist to a second netlist, the first netlist corresponding to a first semiconductor process technology (SPT), the second first netlist corresponding to a second SPT, the first and second netlists each representing a same circuit design, the reducing errors including: inspecting a timing constraint list corresponding to the second netlist for addition candidates; generating a first version of the second netlist having a first number of comparison points relative to a logic equivalence check (LEC) context, the first number of comparison points being based on the addition candidates; performing a LEC between the first netlist and the first version of the second netlist, thereby identifying migration errors; and revising the second netlist to reduce the migration errors, thereby resulting in a second version of the second netlist.
-
公开(公告)号：US11496417B2
公开(公告)日：2022-11-08
申请号：US16879567
申请日：2020-05-20
Inventor： Ravi Venugopalan , Sandeep Kumar Goel , Yun-Han Lee
IPC: H04L49/109 , H04L45/00 , H04L45/28
Abstract: A network-on-chip (NoC) system includes a default communication path between a master device and a slave device, and a backup communication path between the master device and the slave device. The default communication path is configured to work in a normal operation state of the chip. The backup communication path is configured to replace the default communication path when a fault arises in the default communication path.
-
Patent Agency Ranking
公开(公告)号：US11386253B2
公开(公告)日：2022-07-12
申请号：US16901641
申请日：2020-06-15
Inventor： Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
IPC: G06F30/333 , G01R31/3185 , G01R31/317 , G06F30/00
Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.
-
公开(公告)号：US11379643B2
公开(公告)日：2022-07-05
申请号：US17122769
申请日：2020-12-15
Inventor： Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
IPC: G06F30/327 , G06F30/398 , G06F30/3308 , G06F30/333 , G06F119/18 , G06F119/02
Abstract: A method executed at least partially by a processor includes creating a plurality of groups of paths from a plurality of paths in an integrated circuit (IC) layout diagram. Each group among the plurality of groups has a dominant feature among a plurality of features of the plurality of paths. The dominant features of the plurality of groups are different from each other. The method further includes testing at least one path in a group among the plurality of groups. The method also includes, in response to the testing indicating that the at least one path fails, modifying at least one of the IC layout diagram, at least a portion of at least one library having cells included in the IC layout diagram, or a manufacturing process for manufacturing an IC corresponding to the IC layout diagram.
-
公开(公告)号：US20200311329A1
公开(公告)日：2020-10-01
申请号：US16901641
申请日：2020-06-15
Inventor： Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
IPC: G06F30/333 , G01R31/3185 , G01R31/317 , G06F30/00
Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.
-
公开(公告)号：US09647028B2
公开(公告)日：2017-05-09
申请号：US15194961
申请日：2016-06-28
Inventor： Sandeep Kumar Goel , Yun-Han Lee
CPC classification number: H01L27/14687 , H01L21/78 , H01L25/50 , H01L27/14609 , H01L27/14632 , H01L27/14634 , H01L27/1469 , H04N5/367 , H04N5/378
Abstract: A method of forming a wafer on wafer (WOW) stack includes forming a predetermined array of connecting elements on a surface of a first wafer, the first wafer including dies of a first type. The dies of the first type have a first functionality. The method further includes bonding a second wafer to the first wafer using the predetermined array of connecting elements, the second wafer including dies of a second type. The dies of the second type have a separate functionality different from the first functionality. Bonding the second wafer to the first wafer comprises bonding an integer number of dies of the second type to a corresponding die of the first type. A total area of the dies of the second type bonded to the corresponding die of the first type is less than or equal to an area of the corresponding die of the first type.
-
公开(公告)号：US09514268B2
公开(公告)日：2016-12-06
申请号：US14868525
申请日：2015-09-29
Inventor： Sandeep Kumar Goel , Ashok Mehta
IPC: G06F17/50
CPC classification number: G06F17/5081 , G01R31/2818 , G01R31/2851 , G01R31/2853 , G01R31/318513 , G06F17/5077 , G06F2217/14 , G06F2217/40 , H01L22/00 , H01L22/14 , H01L23/49816 , H01L23/49827 , H01L23/49844 , H01L24/02 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/02331 , H01L2224/02375 , H01L2224/02379 , H01L2224/02381 , H01L2224/0401 , H01L2224/05624 , H01L2224/05647 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2224/81192 , H01L2924/014 , H01L2924/00014 , H01L2924/01029 , H01L2924/01014 , H01L2924/01047 , H01L2924/01011 , H01L2924/00012
Abstract: A method includes receiving a design of an interposer having nets, probe pads, and micro-bumps. The nets connect the micro-bumps. The probe pads are initially unconnected to the nets. The method further includes initializing a first set to logically include the nets; processing the first set such that every net interconnecting more than two micro-bumps is divided into a plurality of nets and every two micro-bumps are interconnected by one net; calculating an untested length for each net in the first set; selecting a net N from the first set wherein the net N has the maximum untested length in the first set, the net N representing at least a portion of a net P of the nets; selecting a pair of probe pads that are unconnected to the nets; and connecting the pair of probe pads to the net P by two dummy nets.
Abstract translation: 一种方法包括接收具有网，探针垫和微凸块的插入件的设计。 网络连接微型凸块。 探针垫最初与网不连接。 该方法还包括初始化第一组以逻辑地包括网; 处理第一组，使得互连多于两个微凸块的每个网分成多个网，并且每两个微凸块由一个网互连; 计算第一组中每个网络的未测试长度; 从第一组中选择净N，其中净N具有第一组中的最大未测试长度，网N表示网的净P的至少一部分; 选择一对与网不连接的探针垫; 并通过两个虚拟网将一对探针焊盘连接到网P上。
-
-
-
-
-
-
-
-
-
Search Results
62
records
(took 0.053 seconds)
