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公开(公告)号：US12131109B2
公开(公告)日：2024-10-29
申请号：US18513349
申请日：2023-11-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-Hung Lin , Yuan-Te Hou , Chung-Hsing Wang
IPC: G06F30/30 , G06F30/39 , G06F30/392 , G06F30/394 , G06F30/396 , G06F30/398 , G06F119/06 , G06F119/12
CPC classification number: G06F30/392 , G06F30/39 , G06F30/394 , G06F30/396 , G06F30/398 , G06F2119/06 , G06F2119/12
Abstract: A partitioning method for partitioning a group of power-ground (PG) cells is disclosed. The method includes: placing at least one out-boundary PG cell on a substrate, wherein power strips of the at least one out-boundary PG cell are aligned with corresponding power rails on the substrate; and placing at least one in-boundary PG cell on the substrate, wherein power strips of the at least one in-boundary PG cell are aligned with corresponding power rails on the substrate.
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公开(公告)号：US20240354486A1
公开(公告)日：2024-10-24
申请号：US18758851
申请日：2024-06-28
Inventor： Chao Tong , Qingwen Deng
IPC: G06F30/398 , G06F30/327 , G06F30/392 , G06F30/394 , G06N7/02
CPC classification number: G06F30/398 , G06F30/327 , G06F30/392 , G06F30/394 , G06N7/023
Abstract: Systems and methods include receiving a functional integrated circuit design and generating a plurality of place and route (PnR) layouts based on the received functional integrated circuit design and one or more integrated circuit floorplans may be generated. One or more fuzzy logic rules may be applied to analyze attributes associated with each of the generated PnR layouts, and a PnR layout of the plurality of PnR layouts having an area utilization complying with the one or more fuzzy logic rules may be generated.
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公开(公告)号：US20240354484A1
公开(公告)日：2024-10-24
申请号：US18537878
申请日：2023-12-13
Applicant: Foundation for Research and Business, Seoul National University of Science and Technology
Inventor： Jae Won NAM , Jin Won HYUN
IPC: G06F30/398
CPC classification number: G06F30/398 , G06F2111/06
Abstract: Disclosed herein are integrated circuit design system and method including: a genetic algorithm model unit configured to form a first parent generation using a performance simulation result for an arbitrary integrated circuit design point, form a child generation from the first parent generation using a genetic algorithm, form a surrounding design point based on the first parent generation as a mutant generation, and then select N points with the highest performance among the first parent generation, the child generation, and the mutant generation as a second parent generation; a comparison unit configured to compare a design range of the second parent generation and a preset reference range; and a regression model unit configured to train a regression model using the design range of the second parent generation when a design range of the second parent generation is narrower than or equal to the preset reference range.
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公开(公告)号：US12124789B2
公开(公告)日：2024-10-22
申请号：US17645093
申请日：2021-12-20
Applicant: International Business Machines Corporation
Inventor： Gi-Joon Nam , Jinwook Jung , Alexey Y. Lvov , Lakshmi N. Reddy , Hua Xiang , Rongjian Liang
IPC: G06F30/398
CPC classification number: G06F30/398
Abstract: Techniques regarding parameter tuning for an EDA protocol are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a tuning component that tunes an electronic design automation protocol via a cooperative co-evolutionary optimization framework that shares parameter knowledge across multiple stages of the electronic design automation protocol.
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5.发明公开
公开(公告)号：US20240346226A1
公开(公告)日：2024-10-17
申请号：US18683459
申请日：2021-08-24
Applicant: Siemens Industry Software Inc.
Inventor： Azat Latypov , Young Chang Kim , Germain Louis Fenger
IPC: G06F30/398
CPC classification number: G06F30/398
Abstract: A computing system may include a quantifier determination engine configured to determine a defectivity quantifier for a lithographical circuit fabrication process performed with a target value for a process parameter, including by modifying the target value to obtain an off-target value for the process parameter, determining a defectivity quantifier for the lithographical circuit fabrication process performed with the off-target value, and extrapolating the defectivity quantifier for the lithographical circuit fabrication process performed with the target value from the determined defectivity quantifier for the lithographical circuit fabrication process performed with the off-target value. The computing system may also include a quantifier provision engine configured to provide the determined defectivity quantifier for assessment of the lithographical circuit fabrication process.
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公开(公告)号：US20240338511A1
公开(公告)日：2024-10-10
申请号：US18746888
申请日：2024-06-18
Inventor： Sheng-Hsiung CHEN , Wen-Hao CHEN , Hung-Chih OU , Chun-Yao KU , Shao-Huan WANG
IPC: G06F30/398 , G06F30/3315 , G06F30/337 , G06F30/392 , G06F30/396 , G06F115/06 , G06F119/06 , G06F119/12
CPC classification number: G06F30/398 , G06F30/3315 , G06F30/337 , G06F30/396 , G06F30/392 , G06F2115/06 , G06F2119/06 , G06F2119/12
Abstract: A multi-bit flip-flop includes a first flip-flop and a second flip-flop. The first flip-flop has a first driving capability. The first flip-flop includes a first set pin configured to receive a first set signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second set pin configured to receive the first set signal, and the first set pin and the second set pin are coupled together. The first flip-flop and the second flip-flop are configured to share at least a first clock pin.
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公开(公告)号：US20240330560A1
公开(公告)日：2024-10-03
申请号：US18617549
申请日：2024-03-26
Applicant: CELLIXSOFT CORPORATION
Inventor： Ke DING , Zhong DING , Chongxi ZHANG
IPC: G06F30/392 , G06F30/398
CPC classification number: G06F30/392 , G06F30/398
Abstract: A method and a device for generating an integrated circuit layout are provided. The method includes: acquiring feature information corresponding to multiple components in a first layout, and determining multiple components as target components respectively, the feature information at least includes a type, a size, a layer, and a position of each component; generating default patterns corresponding to the target components based on types of the target components; generating a featureless layout by using the feature information corresponding to the target components as parameter information of the default patterns; acquiring a process rule; based on the process rule, adjusting the parameter information of the default patterns to obtain an adjusted featureless layout; and obtaining a second layout, based on the adjusted featureless layout and the process rule.
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公开(公告)号：US12106034B2
公开(公告)日：2024-10-01
申请号：US18447455
申请日：2023-08-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Lin Chuang , Henry Lin , Szu-Ju Huang , Yin-An Chen , Amos Hong
IPC: G06F30/398 , G06F30/327 , G06F30/392 , G06F30/394 , G06N20/00
CPC classification number: G06F30/398 , G06F30/327 , G06F30/392 , G06F30/394 , G06N20/00
Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.
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公开(公告)号：US12106033B2
公开(公告)日：2024-10-01
申请号：US18341545
申请日：2023-06-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Cheok-Kei Lei , Zhe-Wei Jiang , Chi-Yu Lu , Yi-Hsin Ko , Chi-Lin Liu , Hui-Zhong Zhuang
IPC: G06F30/398 , G06F30/327 , G06F30/392 , H01L23/52 , H01L23/522
CPC classification number: G06F30/398 , G06F30/327 , G06F30/392 , H01L23/52 , H01L23/5222
Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.
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10.发明授权
公开(公告)号：US12106030B2
公开(公告)日：2024-10-01
申请号：US17452357
申请日：2021-10-26
Inventor： Hiranmay Biswas , Chung-Hsing Wang , Kuo-Nan Yang , Yi-Kan Cheng
IPC: G06F30/394 , G06F30/398 , H01L27/02 , G06F119/06 , H01L27/118
CPC classification number: G06F30/394 , G06F30/398 , H01L27/0207 , G06F2119/06 , H01L27/11807
Abstract: A method (of generating a revised layout diagram of a conductive line structure for an IC) including: for a first set of pillar patterns that represents portions of an M(i) layer of metallization and where i is a non-negative number, the first set including first and second pillar patterns which extend in a first direction, are non-overlapping of each other with respect to the first direction, are aligned with each other and have a first distance of separation, determining a first distance of separation as between corresponding immediately adjacent members of the first set; recognizing that the first distance is less than a transverse routing (TVR) separation threshold for an M(i+j) layer of metallization, where j is an integer and j≥2; and increasing the first distance so as to become a second distance which is greater than the TVR separation threshold of the M(i+j) layer.
