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公开(公告)号：US12229483B2
公开(公告)日：2025-02-18
申请号：US18350129
申请日：2023-07-11
Inventor： Sandeep Kumar Goel , Ankita Patidar , Yun-Han Lee
IPC: G06F30/323 , G03F1/70 , G06F30/3323 , G06F30/392 , G06F30/394 , G06F119/12
Abstract: A method (of manufacturing a semiconductor device) includes: migrating a circuit design from a first netlist corresponding with a first semiconductor process technology (SPT) to a second netlist corresponding with a second SPT, at least the second netlist being stored on a non-transitory computer-readable medium, the migrating including: generating first versions correspondingly of the first and second netlists; abstracting selected components in the first version of the second netlist and correspondingly in the first version of the second netlist to form corresponding second versions of the second and first netlists; performing a logic equivalence check (LEC) between the second versions of the first and second netlists, thereby identifying migration errors; and revising the second version of the second netlist to reduce the migration errors, thereby resulting in a third version of the second netlist.
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公开(公告)号：US20240394440A1
公开(公告)日：2024-11-28
申请号：US18790464
申请日：2024-07-31
Inventor： Kai-Yuan TING , Hsin-Cheng Chen , Sandeep Kumar Goel , Mei Wong , Yun-Han Lee
IPC: G06F30/20 , G06F30/367 , G06F119/06
Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation and modeling of function safety and fault management of an electronic device. A method for simulating a safety circuit includes providing an electronic architectural design to perform one or more functional behaviors of the electronic device in accordance with an electronic design specification. The method further includes modeling the safety circuit of the electronic architectural design and one or more other electronic circuits of the electronic architectural design that communicate with the safety circuit. The method further includes simulating, using the modeling, operation of the safety circuit while the electronic architectural design is performing the one or more functional behaviors. The method also includes determining whether the simulated operation of the safety circuit satisfies the electronic design specification.
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公开(公告)号：US12095711B2
公开(公告)日：2024-09-17
申请号：US18190881
申请日：2023-03-27
Inventor： Huan-Neng Chen , William Wu Shen , Chewn-Pu Jou , Feng Wei Kuo , Lan-Chou Cho , Tze-Chiang Huang , Jack Liu , Yun-Han Lee
CPC classification number: H04L5/14 , H04W52/0261 , Y02D30/70
Abstract: An integrated circuit includes first through fourth devices positioned over one or more substrates, a first radio frequency interconnect (RFI) including a first transmitter included in the first device, a first receiver included in the second device, and a first guided transmission medium coupled to each of the first transmitter and the first receiver, a second RFI including a second transmitter included in the first device, a second receiver included in the third device, and a second guided transmission medium coupled to each of the second transmitter and the second receiver, and a third RFI including a third transmitter included in the first device, a third receiver included in the fourth device, and the second guided transmission medium coupled to each of the third transmitter and the third receiver.
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公开(公告)号：US11879933B2
公开(公告)日：2024-01-23
申请号：US17393232
申请日：2021-08-03
Inventor： Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
IPC: G01R31/02 , G06F30/398 , G01R31/317 , G06F119/08 , G01R31/28
CPC classification number: G01R31/2855 , G01R31/31721 , G06F30/398 , G06F2119/08
Abstract: A method of testing an integrated circuit on a test circuit board includes performing, by a processor, a simulation of a first heat distribution throughout an integrated circuit design, manufacturing the integrated circuit according to the integrated circuit design, and simultaneously performing a burn-in test of the integrated circuit and an automated test of the integrated circuit. The burn-in test has a minimum burn-in temperature of the integrated circuit and a burn-in heat distribution across the integrated circuit. The integrated circuit design corresponds to the integrated circuit. The integrated circuit is coupled to the test circuit board. The integrated circuit includes a set of circuit blocks and a first set of heaters.
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公开(公告)号：US11343433B2
公开(公告)日：2022-05-24
申请号：US16595088
申请日：2019-10-07
Inventor： Sandeep Kumar Goel , Yun-Han Lee , Ashok Mehta
Abstract: An apparatus includes an image sensor having a light sensing region, the light sensing region being partitioned into a plurality of sub-regions, a first sub-region of the plurality of sub-regions has a first size, a second sub-region of the plurality of sub-regions has a second size different from the first size, and the second sub-region partially overlaps with the first sub-region. The apparatus further includes a processor coupled with the image sensor, wherein the processor includes a plurality of pixel processing units, and each processing unit of the plurality of processing units is configured to generate a processed image based on an image captured by a corresponding sub-region of the plurality of sub-regions. The apparatus further includes a plurality of lenses configured to focus incident light onto the image sensor.
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Patent Agency Ranking
公开(公告)号：US11216376B2
公开(公告)日：2022-01-04
申请号：US16587215
申请日：2019-09-30
Inventor： Hsien-Hsin Sean Lee , William Wu Shen , Yun-Han Lee
IPC: G11C8/00 , G06F12/0804 , G11C5/04 , G11C5/02 , G06F12/0891 , G11C7/22
Abstract: A memory circuit includes a first memory circuit formed of a first die or a set of stacked dies. The memory circuit further includes a second memory circuit formed of a second die, the second memory circuit comprising one or more sets of memory cells of a second type and each set of the memory cells of the second type comprising multiple cache sections. The first die or the set of stacked dies are stacked over the second die, wherein the second die further includes a first plurality of I/O terminals and a second plurality of I/O terminals, the first plurality of I/O terminals being electrically coupled to the first memory circuit, and the second plurality of I/O terminals being electrically isolated from the first memory circuit.
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公开(公告)号：US20210335668A1
公开(公告)日：2021-10-28
申请号：US17371438
申请日：2021-07-09
Inventor： Bo-Jr Huang , William Wu Shen , Chin-Her Chien , Chin-Chou Liu , Yun-Han Lee
IPC: H01L21/768 , H01Q1/22 , H01Q9/04 , H01Q1/48 , H01L23/498 , H01L23/66 , H01L21/48 , H01L23/48 , H01L23/00
Abstract: The present disclosure relates to a semiconductor module. The semiconductor module includes an excitable element located on a first side of a substrate. A first ground structure is disposed between the first side of the substrate and the excitable element. The first ground structure includes a conductive via extending through the substrate and an interconnect disposed over a topmost surface of the conductive via facing away from the substrate. A second ground structure is located on a second side of the substrate, opposing the first side, and electrically coupled to the first ground structure.
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公开(公告)号：US10430334B2
公开(公告)日：2019-10-01
申请号：US15248093
申请日：2016-08-26
Inventor： Hsien-Hsin Sean Lee , William Wu Shen , Yun-Han Lee
IPC: G11C8/00 , G06F12/0804 , G11C5/02 , G11C5/04 , G06F12/0891 , G11C7/22
Abstract: A method of operating a memory circuit is disclosed. The memory circuit comprises a primary memory and a cache memory. The primary memory has P access channels of Q bits of channel bandwidth, and the cache memory has P subsets of Q*N memory cells, wherein P and Q are integers greater than 1, and N is a positive integer. The method includes determining, in response to a command for reading first and second data accessible through first and second access channels respectively, if a valid duplication of the first and second data is stored in the cache memory. If yes, the method further includes storing a duplication of Q*n bits of consecutively addressed data from each of the first and second access channels to the cache memory, n being an integer from 1 to N. Otherwise, the method further includes outputting the first and second data from the cache memory.
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公开(公告)号：US20190123019A1
公开(公告)日：2019-04-25
申请号：US16223449
申请日：2018-12-18
Inventor： Chen-Hua Yu , Shang-Yun Hou , Yun-Han Lee
IPC: H01L23/00 , H01L25/065 , H01L23/48 , H01L27/24 , H01L27/28 , H01L27/06 , H01L23/522 , H01L27/12 , H01L25/10 , H01L21/48 , H01L23/538 , H01L49/02 , G05F3/02 , H01L23/28
CPC classification number: H01L24/97 , G05F3/02 , H01L21/4846 , H01L23/28 , H01L23/481 , H01L23/5226 , H01L23/5227 , H01L23/5389 , H01L24/25 , H01L25/0652 , H01L25/105 , H01L27/0688 , H01L27/124 , H01L27/2481 , H01L27/283 , H01L28/10 , H01L2224/16225 , H01L2225/0651 , H01L2225/06541 , H01L2225/06582 , H01L2225/1041 , H01L2225/1058 , H01L2225/107
Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.
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公开(公告)号：US09697319B2
公开(公告)日：2017-07-04
申请号：US14679843
申请日：2015-04-06
Inventor： Yun-Han Lee , Wu-An Kuo
IPC: G06F17/50
CPC classification number: G06F17/5072
Abstract: A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.
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