公开(公告)号：US20190237378A1

公开(公告)日：2019-08-01

申请号：US16382323

申请日：2019-04-12

申请人： DENSO CORPORATION

发明人： Wataru KOBAYASHI ,  Kazuki KODA

IPC分类号： H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L23/3142 ,  B23K26/00 ,  B23K26/354 ,  B29C65/00 ,  H01L21/4821 ,  H01L23/28 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/50 ,  H01L24/32 ,  H01L2224/27013 ,  H01L2224/32245

摘要： An electronic device includes: a support member that has a metallic placement surface joined to the conductive bonding layer, and a metallic sealing surface provided on an outer side of the placement surface in an in-plane direction of the placement surface to adjoin the placement surface and to surround the placement surface; and a resin member, which is a synthetic resin molded article, joined to the sealing surface and covering the electronic component. The sealing surface includes a rough surface having a plurality of laser irradiation marks having a substantially circular shape. The rough surface includes a first region and a second region. The second region has a higher density of the laser irradiation marks in the in-plane direction than the first region.

公开(公告)号：US20190131213A1

公开(公告)日：2019-05-02

申请号：US16091154

申请日：2016-06-03

申请人： Mitsubishi Electric Corporation

发明人： Arata IIZUKA ,  Korehide OKAMOTO ,  Natsuki TSUJI

IPC分类号： H01L23/488 ,  H01L23/36 ,  H01L23/053 ,  H01L23/16

CPC分类号： H01L23/488 ,  H01L23/053 ,  H01L23/16 ,  H01L23/28 ,  H01L23/36 ,  H01L23/48 ,  H01L25/07 ,  H01L25/18 ,  H01L2224/40

摘要： The present invention relates to a semiconductor device module which includes: a semiconductor device including a top electrode and a bottom electrode; a substrate on which the bottom electrode of the semiconductor device is bonded; a heat sink on which the substrate is mounted; a lead electrode through which a main current of the semiconductor device flows; an insulating case disposed to enclose the substrate; and a retainer disposed in a cantilevered manner in the insulating case, the retainer supporting the lead electrode, wherein the lead electrode has one end brazed to the top electrode of the semiconductor device, and another end side inserted into a wall of the insulating case, and the retainer is engaged on the one end of the lead electrode to restrict movement of the lead electrode.

公开(公告)号：US20190123019A1

公开(公告)日：2019-04-25

申请号：US16223449

申请日：2018-12-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Shang-Yun Hou ,  Yun-Han Lee

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L23/48 ,  H01L27/24 ,  H01L27/28 ,  H01L27/06 ,  H01L23/522 ,  H01L27/12 ,  H01L25/10 ,  H01L21/48 ,  H01L23/538 ,  H01L49/02 ,  G05F3/02 ,  H01L23/28

CPC分类号： H01L24/97 ,  G05F3/02 ,  H01L21/4846 ,  H01L23/28 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/5389 ,  H01L24/25 ,  H01L25/0652 ,  H01L25/105 ,  H01L27/0688 ,  H01L27/124 ,  H01L27/2481 ,  H01L27/283 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107

摘要： A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

公开(公告)号：US20190057943A1

公开(公告)日：2019-02-21

申请号：US15680669

申请日：2017-08-18

申请人： Advanced Semiconductor Engineering Korea, Inc.

发明人： Seokbong KIM ,  Sunju PARK ,  Hyoungjoon JIN

IPC分类号： H01L23/66 ,  H01L23/31 ,  H01L23/552

CPC分类号： H01L23/3736 ,  H01L23/28 ,  H01L23/3121 ,  H01L23/315 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/1615 ,  H01L2924/16251 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/30111 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/81

摘要： A semiconductor package device comprises a substrate, a die, an encapsulant and an antenna layer. The substrate has a top surface and a bottom surface opposite to the top surface. The die is disposed on the top surface of the substrate. The encapsulant is disposed on the top surface of the substrate and surrounds the die. The encapsulant has a top surface and defines a recess on the top surface of the encapsulant. The antenna layer is disposed on the top surface of the encapsulant and extends within the recess on the top surface of the encapsulant.

公开(公告)号：US20180226893A1

公开(公告)日：2018-08-09

申请号：US15943465

申请日：2018-04-02

申请人： Power Integrations, Inc.

发明人： Balu Balakrishnan ,  David Michael Hugh Matthews

IPC分类号： H02M3/335 ,  H01L23/495 ,  H02M7/00 ,  H01L23/58 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31 ,  H01L23/28 ,  H04B5/00 ,  H01L23/48 ,  H01L23/00

CPC分类号： H02M3/33507 ,  H01L23/28 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/552 ,  H01L23/58 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/45099 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/4911 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/14253 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H02M3/33523 ,  H02M3/33592 ,  H02M7/003 ,  H02M7/2176 ,  H04B5/0031 ,  H04B5/0081 ,  Y02B70/1475 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： An integrated circuit package includes an encapsulation and a lead frame. A portion of the lead frame is disposed within the encapsulation. The lead frame includes a first conductor having an inner conductive loop disposed substantially within the encapsulation and a second conductor galvanically isolated from the first conductor. The second conductor includes an outer conductive loop disposed substantially within the encapsulation proximate to and magnetically coupled to the inner conductive loop to provide a communication link between the first and second conductors.

公开(公告)号：US20180204781A1

公开(公告)日：2018-07-19

申请号：US15919367

申请日：2018-03-13

申请人： Murata Manufacturing Co., Ltd.

发明人： Yoshihito OTSUBO

IPC分类号： H01L23/31 ,  H01L25/04 ,  H01L25/18 ,  H01L23/00 ,  H05K9/00

CPC分类号： H01L23/3121 ,  H01L23/28 ,  H01L23/552 ,  H01L24/16 ,  H01L24/82 ,  H01L25/04 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0216 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/181 ,  H05K3/284 ,  H05K9/0022 ,  H05K9/0081 ,  H05K9/0084 ,  H05K2201/09972 ,  H05K2203/1322 ,  H01L2924/00012 ,  H01L2224/13099

摘要： A high-frequency module la includes: a wiring substrate 2; a plurality of components 3a and 3b that are mounted on an upper surface 2a of the wiring substrate 2; a sealing resin layer 4 that is stacked on the upper surface 2a of the wiring substrate 2; a shield film 6 that covers a surface of the sealing resin layer 4; and a shield wall 5 that is provided in the sealing resin layer 4. The shield wall 5 is formed of two shield wall element bodies 5a and 5b that have straight line shapes in a plan view, and the two shield wall element bodies 5a and 5b are arranged such that the shield wall element bodies each have one end surface that is not exposed at a different peripheral side surface 4b of the sealing resin layer 4.

公开(公告)号：US20180182714A1

公开(公告)日：2018-06-28

申请号：US15845256

申请日：2017-12-18

申请人： EVERSPIN TECHNOLOGIES, INC.

发明人： De Jun HUANG ,  Quan Bang LI

IPC分类号： H01L23/552 ,  H01L49/02 ,  H01L21/56 ,  H01L21/28 ,  H01L23/28 ,  H01L23/13 ,  H01L23/00 ,  H05K1/02 ,  G11C16/04 ,  G11C17/08

CPC分类号： H01L23/552 ,  G11C16/0433 ,  G11C17/08 ,  H01L21/28273 ,  H01L21/561 ,  H01L23/13 ,  H01L23/28 ,  H01L24/97 ,  H01L25/0657 ,  H01L49/02 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06575 ,  H05K1/0237

摘要： The present disclosure is drawn to, among other things, a method of forming a semiconductor shield from a stock material having a thickness. In some aspects the methods includes providing a first layer of material on a first surface of the stock material, wherein at least a portion of the first layer of material includes a first window that exposes a portion of the first surface; providing a second layer of material on a second surface of the stock material, wherein the second surface of the stock material is spaced from the first surface by the thickness of the stock material, and wherein at least portion of the second layer of material includes a second window that exposes a portion of the second surface; and selectively removing a portion of the stock material exposed at the first or second windows, wherein the portion removed includes less than an entirety of the thickness of the stock material.

公开(公告)号：US20180166491A1

公开(公告)日：2018-06-14

申请号：US15580552

申请日：2016-06-02

申请人： SONY CORPORATION

发明人： Masaya NAGATA ,  Kaori TAKIMOTO

IPC分类号： H01L27/146 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L27/14634 ,  H01L21/563 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/28 ,  H01L23/29 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/043 ,  H01L25/065 ,  H01L25/0657 ,  H01L25/07 ,  H01L25/074 ,  H01L25/0756 ,  H01L25/117 ,  H01L25/18 ,  H01L27/14 ,  H01L27/14618 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/1469 ,  H01L2224/05025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92225 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00014

摘要： The present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method that can maintain the mounting reliability of an underfill. A chip is formed by a circuit of an imaging element being produced on a Si substrate that is a first substrate and a second substrate being produced on an adhesive formed on the circuit. In this event, a photosensitive material is formed around the chip after the chip is mounted on a mounting substrate by a solder ball or in the state of the chip, then an underfill is formed, and then only the photosensitive material is dissolved. The present disclosure can be applied to, for example, a CMOS solid-state imaging sensor used for an imaging device such as a camera.

公开(公告)号：US20180166387A1

公开(公告)日：2018-06-14

申请号：US15840483

申请日：2017-12-13

申请人： Murata Manufacturing Co., Ltd.

发明人： Hideki Matsui ,  Yuji Takematsu

IPC分类号： H01L23/535 ,  H03F3/195 ,  H03F3/21 ,  H01L23/66

CPC分类号： H01L23/535 ,  H01L23/00 ,  H01L23/12 ,  H01L23/28 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/66 ,  H01L25/04 ,  H01L25/18 ,  H01L2223/6644 ,  H03F3/195 ,  H03F3/21 ,  H03F3/213 ,  H03F2200/294 ,  H03F2200/451 ,  H04B1/38 ,  H04B1/40

摘要： A transmit-and-receive module includes a wiring substrate, a low-noise amplifier, a power amplifier, an insulating resin, and a conductive shield. The wiring substrate has a first surface and a second surface which is a back side of the first surface. The low-noise amplifier includes a first signal terminal and a first ground terminal. The first signal terminal is surface-mounted on the first surface. The power amplifier includes a second signal terminal and a second ground terminal. The second signal terminal and the second ground terminal are surface-mounted on the first surface. The insulating resin covers the low-noise amplifier and the power amplifier. The conductive shield covers a surface of the insulating resin. The first ground terminal is connected to the conductive shield.

公开(公告)号：US09991213B2

公开(公告)日：2018-06-05

申请号：US15290545

申请日：2016-10-11

申请人： Rohm Co., Ltd.

发明人： Yasumasa Kasuya ,  Motoharu Haga ,  Shoji Yasunaga

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L23/28 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L23/31

CPC分类号： H01L23/562 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4842 ,  H01L21/565 ,  H01L22/12 ,  H01L23/28 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49555 ,  H01L23/49582 ,  H01L23/564 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/27013 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A resin-encapsulated semiconductor device having a semiconductor chip which is prevented from being damaged. The resin-encapsulated semiconductor device (100) comprises a semiconductor chip (1) including a silicon substrate, a die pad (10) to which the semiconductor chip (1) is secured through a first solder layer (2), a resin-encapsulating layer (30) encapsulating the semiconductor chip (1), and lead terminals (21) electrically connected to the semiconductor chip (1) and including inner lead portion (21b) covered with the resin-encapsulating layer (30). The lead terminals (21) are made of copper or a copper alloy. The die pad (10) is made of 42 alloy or a cover alloy and has a thickness (about 0.125 mm) less than the thickness (about 0.15 mm) of the lead terminals (21).