公开(公告)号：US11955574B2

公开(公告)日：2024-04-09

申请号：US15725509

申请日：2017-10-05

Applicant: International Business Machines Corporation

Inventor： Ning Li ,  Devendra Sadana ,  Ghavam G. Shahidi ,  Chitra K. Subramanian

IPC: H01L31/05 ,  H01L25/04 ,  H01L31/02

CPC classification number: H01L31/0508 ,  H01L25/042 ,  H01L25/043 ,  H01L31/02019 ,  H01L31/02021 ,  H01L31/0504

Abstract: A multi-level photovoltaic cell comprises a substrate layer and a plurality of photovoltaic cells positioned above the substrate layer. Each photovoltaic cell has a top contact layer and a bottom contact layer connected in series such that the top contact layer of the first photovoltaic cell is connected to the bottom contact layer of a next photovoltaic cell until the last photovoltaic cell is connected. A different voltage is output between the substrate layer and the top contact layer of each photovoltaic cell. Another multi-level photovoltaic cell comprises a substrate layer and a plurality of photovoltaic cells stacked vertically above the substrate layer. Each photovoltaic cell comprises an active layer separated from the next photovoltaic cell by an etch stop layer until a last photovoltaic cell is reached. A different voltage is output between the substrate layer and the active layer of each photovoltaic cell.

公开(公告)号：US11915999B2

公开(公告)日：2024-02-27

申请号：US18103865

申请日：2023-01-31

Applicant: Infineon Technologies AG

Inventor： Tomasz Naeve ,  Ralf Otremba ,  Thorsten Scharf ,  Markus Dinkel ,  Martin Gruber ,  Elvir Kahrimanovic

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/40 ,  H01L25/065 ,  H01L25/075 ,  H01L25/04 ,  H02P27/06

CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4012 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L25/043 ,  H01L25/0655 ,  H01L25/0756 ,  H01L2924/181 ,  H02P27/06 ,  H02P2201/03

Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.

公开(公告)号：US20240056082A1

公开(公告)日：2024-02-15

申请号：US18231415

申请日：2023-08-08

Applicant: iCometrue Company Ltd.

Inventor： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC: H03K19/173 ,  H10B80/00 ,  H01L25/04 ,  H03K3/037

CPC classification number: H03K19/173 ,  H10B80/00 ,  H01L25/043 ,  H03K3/037

Abstract: A multi-chip package includes a first semiconductor integrated-circuit (IC) chip comprising a first input/output (I/O) circuit therein; and an input/output (I/O) integrated-circuit (IC) chip comprising a second input/output (I/O) circuit therein coupling to the first input/output (I/O) circuit, a third input/output (I/O) circuit therein, a voltage-level shift-up circuit therein configured to shift data from a first voltage level at a first node thereof coupling to the second input/output (I/O) circuit to a second voltage at a second node thereof coupling to the third input/output (I/O) circuit and a voltage-level shift-down circuit therein configured to shift data from the second voltage level at the second node coupling to the third input/output (I/O) circuit to the first voltage level at the first node coupling to the second input/output (I/O) circuit, wherein the second voltage level is higher than the first voltage level.

公开(公告)号：US11830845B2

公开(公告)日：2023-11-28

申请号：US17867554

申请日：2022-07-18

Applicant: Adeia Semiconductor Solutions LLC

Inventor： Hiroaki Sato ,  Teck-Gyu Kang ,  Belgacem Haba ,  Philip R. Osborn ,  Wei-Shun Wang ,  Ellis Chau ,  Ilyas Mohammed ,  Norihito Masuda ,  Kazuo Sakuma ,  Kiyoaki Hashimoto ,  Kurosawa Inetaro ,  Tomoyuki Kikuchi

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L25/04 ,  H01L27/146 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L24/18 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4952 ,  H01L23/49811 ,  H01L24/73 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L27/14618 ,  H01L27/14625 ,  H01L21/56 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/45 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1713 ,  H01L2224/17179 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45101 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/4824 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48464 ,  H01L2224/49105 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/107 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01049 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19107

Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

公开(公告)号：US11764248B2

公开(公告)日：2023-09-19

申请号：US17506885

申请日：2021-10-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng Yu Huang ,  Chun-Hao Chuang ,  Chien-Hsien Tseng ,  Kazuaki Hashimoto ,  Keng-Yu Chou ,  Wei-Chieh Chiang ,  Wen-Hau Wu

IPC: H01L27/146 ,  H01L23/552 ,  H01L23/64 ,  H01L25/04

CPC classification number: H01L27/14643 ,  H01L23/552 ,  H01L23/64 ,  H01L25/043 ,  H01L27/1469 ,  H01L27/14621 ,  H01L27/14629 ,  H01L27/14632 ,  H01L27/14636

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes an image sensor disposed within a first substrate. A first band-pass filter and a second band-pass filter are disposed on the first substrate. A dielectric structure is disposed on the first substrate. The dielectric structure is laterally between the first band-pass filter and the second band-pass filter and laterally abuts the first band-pass filter and the second band-pass filter.

公开(公告)号：US20180152132A1

公开(公告)日：2018-05-31

申请号：US15878981

申请日：2018-01-24

Applicant: Chaitanya Karamchedu

Inventor： Chaitanya Karamchedu

IPC: H02S20/10 ,  H01L25/04

CPC classification number: H02S20/10 ,  H01L25/043 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed embodiments include multi-plane photovoltaic modules and/or solar panel arrangements, as well as solar farms constituted with such arrangements/modules. In embodiments, a solar panel arrangement may include a first solar panel having a first plurality of solar photovoltaic modules, disposed at a first plane; and a second solar panel having a second plurality of solar photovoltaic modules, disposed at a second plane, vertically offset from the first plane. Similarly, in embodiments, a photovoltaic module may include a first substrate having a first plurality of photovoltaic cells, disposed at a first plane; and a second substrate having a second plurality of photovoltaic cells, disposed at a second plane, vertically offset from the first plane. Other embodiments may be described and claimed.

公开(公告)号：US20180005990A1

公开(公告)日：2018-01-04

申请号：US15197494

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Saeed S. Shojaie

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L25/043 ,  H01L25/0756 ,  H01L25/117 ,  H01L25/50 ,  H01L2224/023 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06586

Abstract: Apparatuses, methods and storage medium associated with integrated packaging for a stack of semiconductor dice of different sizes are disclosed herein. In embodiments, an apparatus including dice of different sizes may include a first die having a first side and a second side opposite the first side and a second smaller die having a first side and a second side opposite the first side the second side. The second side of the first die may be smaller than the first side of the second die and may be coupled thereto such that a portion of the first side of the second die is exposed. The apparatus may include wires coupled with and extending from the portion of the first side of the second die through a casing to a redistribution layer coupled with a side of the casing, to electrically couple the dice. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US20170373113A1

公开(公告)日：2017-12-28

申请号：US15693544

申请日：2017-09-01

Applicant: Google Inc.

Inventor： Chung Chun Wan

IPC: H01L27/146 ,  H04N5/378 ,  G01S17/08 ,  H04N5/33 ,  G06T7/50 ,  H01L25/04 ,  H04N9/04 ,  H04N5/3745

CPC classification number: H01L27/14652 ,  G01S17/08 ,  G06T7/50 ,  H01L25/043 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14649 ,  H01L2924/00 ,  H01L2924/0002 ,  H04N5/332 ,  H04N5/37455 ,  H04N5/378 ,  H04N9/045

Abstract: An apparatus is described that includes a first semiconductor chip having a first pixel array. The first pixel array has visible light sensitive pixels. The apparatus includes a second semiconductor chip having a second pixel array. The first semiconductor chip is stacked on the second semiconductor chip such that the second pixel array resides beneath the first pixel array. The second pixel array has IR light sensitive pixels for time-of-flight based depth detection.

公开(公告)号：US09761507B1

公开(公告)日：2017-09-12

申请号：US15092671

申请日：2016-04-07

Applicant: Diodes Incorporated

Inventor： Pin-Hao Huang ,  Tim C. Chen ,  Yeng-Liang Lin ,  Bau Shun Huang

IPC: H01L23/495 ,  H01L25/04 ,  H01L23/373 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49537 ,  H01L25/043 ,  H01L25/0657 ,  H01L2225/06548 ,  H01L2225/06589 ,  H02M7/06

Abstract: A rectifier package is provided, which comprises a first rectifier die having an anode and a cathode conductively bonded to a first conductive film on a first surface. The rectifier package also comprises a second rectifier die having an anode and a cathode conductively bonded to the first conductive film on a second surface, which is opposite to the first surface. The first conductive film is in contact with both anodes or both cathodes of the first rectifier die and the second rectifier die.

公开(公告)号：US09748218B1

公开(公告)日：2017-08-29

申请号：US15434289

申请日：2017-02-16

Applicant: International Business Machines Corporation

Inventor： Philip G. Emma

IPC: H01L23/473 ,  H01L25/00 ,  H01L25/075 ,  H01L33/64 ,  H01L23/46 ,  H01L23/42 ,  H01L23/44 ,  H01L23/02 ,  H01L31/12 ,  H01L21/52

CPC classification number: H01L25/50 ,  H01L21/52 ,  H01L23/02 ,  H01L23/34 ,  H01L23/42 ,  H01L23/44 ,  H01L23/46 ,  H01L23/467 ,  H01L23/473 ,  H01L25/043 ,  H01L25/0756 ,  H01L25/167 ,  H01L27/156 ,  H01L31/12 ,  H01L33/641 ,  H01L33/642 ,  H01L33/648 ,  H01L2933/0033 ,  H01L2933/0066 ,  H01L2933/0075 ,  H04B10/2503

Abstract: In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.