Patent search cpc:"H01L2924/1615" Page 1

1.

发明授权
Manufacturing method of semiconductor device 有权
Title translation: 半导体器件的制造方法

公开(公告)号：US09425088B2

公开(公告)日：2016-08-23

申请号：US13862381

申请日：2013-04-13

Applicant: Fujitsu Semiconductor Limited

Inventor： Takumi Ihara , Seiji Ueno , Joji Fujimori , Yasunori Fujimoto

IPC: H01L21/00 , H01L21/768 , H01L23/552 , H01L25/16 , H01L23/36 , H01L23/367 , H01L23/42 , H01L25/065

CPC classification number: H01L21/76838 , H01L23/36 , H01L23/3675 , H01L23/42 , H01L23/552 , H01L25/0655 , H01L25/16 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81191 , H01L2924/15311 , H01L2924/1615 , H01L2924/16251 , H01L2924/19105 , H01L2924/00

Abstract: A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor.

Abstract translation: 半导体器件包括：衬底; 半导体元件安装在基板上，使得形成有电极的表面被引导到基板; 芯片电容器安装在基板上; 以及覆盖与半导体元件的表面相对的后表面并与芯片电容器的一个端子电极接合的导电材料。

2.

发明授权
Semiconductor package having EMI shielding function and heat dissipation function 有权
Title translation: 具有EMI屏蔽功能和散热功能的半导体封装

公开(公告)号：US08921993B2

公开(公告)日：2014-12-30

申请号：US14153327

申请日：2014-01-13

Applicant: Samsung Electronics Co., Ltd

Inventor： In-Ho Choi , Yong-Hoon Kim , Seong-Ho Shin

IPC: H01L23/52 , H01L23/552

CPC classification number: H01L23/552 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L2224/131 , H01L2224/16225 , H01L2224/2929 , H01L2224/29339 , H01L2224/29387 , H01L2224/29388 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L2924/15192 , H01L2924/15311 , H01L2924/1615 , H01L2924/16251 , H01L2924/16724 , H01L2924/16747 , H01L2924/00012 , H01L2924/014 , H01L2924/00

Abstract: A semiconductor package includes a substrate, a semiconductor chip located on a top surface of the substrate, signal lines formed on the top surface of the substrate and configured to allow different types of signals to input/output thereto/therefrom, a ground line unit formed on the top surface of the substrate and configured to divide the signal lines into signal lines to/from which the same types of signals are input/output to be isolated from one another, barrier walls configured to contact the ground line unit, and a heat dissipation unit disposed on the semiconductor chip, wherein the ground line unit includes diagonal ground lines located in diagonal directions of the substrate about the semiconductor chip, and the heat dissipation unit includes a thermal interface material (TIM) located on a top surface of the semiconductor chip, and a heat dissipation plate configured to cover the TIM and the substrate.

Abstract translation: 半导体封装包括衬底，位于衬底的顶表面上的半导体芯片，形成在衬底的顶表面上并被配置为允许不同类型的信号从其输入/输出的信号线，形成的接地线单元在基板的顶表面上，并且将信号线分成信号线，以使相同类型的信号被输入/输出为彼此隔离的信号线，被配置为接触地线单元的阻挡壁和热量设置在半导体芯片上的散热单元，其中接地线单元包括位于半导体芯片周围的基板的对角线方向的对角线，而散热单元包括位于半导体芯片顶表面上的热界面材料（TIM）芯片，以及配置成覆盖TIM和基板的散热板。

3.

发明授权
Circuit assemblies with multiple interposer substrates, and methods of fabrication 有权

公开(公告)号：US09905507B2

公开(公告)日：2018-02-27

申请号：US15181872

申请日：2016-06-14

Applicant: Invensas Corporation

Inventor： Hong Shen , Zhuowen Sun , Charles G. Woychik , Arkalgud Sitaram

IPC: H01L21/768 , H01L23/498 , H05K1/11 , H01L25/00 , H05K1/18 , H05K1/02 , H05K1/14 , H01L23/538 , H01L25/065 , H01L23/00 , H01L21/683 , H01L25/03 , H01L21/48 , H01L23/31 , H01L21/56

CPC classification number: H01L23/49833 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L21/561 , H01L21/6835 , H01L21/76898 , H01L23/3121 , H01L23/3128 , H01L23/498 , H01L23/49827 , H01L23/49838 , H01L23/538 , H01L23/5381 , H01L23/5383 , H01L23/5385 , H01L23/5389 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/97 , H01L25/03 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L2221/68327 , H01L2224/0401 , H01L2224/04042 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/81203 , H01L2224/81801 , H01L2224/92125 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2225/06589 , H01L2924/00014 , H01L2924/14 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/1615 , H01L2924/16153 , H01L2924/16251 , H01L2924/181 , H05K1/0271 , H05K1/111 , H05K1/141 , H05K1/181 , H01L2924/00012 , H01L2224/81 , H01L2224/85 , H01L2924/014 , H01L2224/83 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

4.

发明申请
BOARD LEVEL SHIELDS WITH VIRTUAL GROUNDING CAPABILITY 有权

公开(公告)号：US20170311438A1

公开(公告)日：2017-10-26

申请号：US15490012

申请日：2017-04-18

Applicant: Laird Technologies, Inc.

Inventor： Mohammadli Khorrami , Paul Francis Dixon , George William Rhyne

IPC: H05K1/02 , H01L23/64 , H01L23/00 , H05K1/18 , H01L23/31 , H01L23/552 , H05K3/30

CPC classification number: H05K1/0216 , H01L23/3114 , H01L23/552 , H01L23/64 , H01L23/642 , H01L23/645 , H01L24/48 , H01L24/85 , H01L2924/141 , H01L2924/1615 , H01L2924/16251 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H01L2924/19107 , H05K1/0233 , H05K1/18 , H05K3/30 , H05K9/0003 , H05K9/0028 , H05K2201/0707 , H05K2201/10015 , H05K2201/1003 , H05K2201/10371 , H05K2201/2018

Abstract: According to various aspects, exemplary embodiments are disclosed of board level shields with virtual grounding capability. In an exemplary embodiment, a board level shield includes one or more resonators configured to be operable for virtually connecting the board level shield to a ground plane or a shielding surface. Also disclosed are exemplary embodiments of methods relating to making board level shields having virtual grounding capability. Additionally, exemplary embodiments are disclosed of methods relating to providing shielding for one or more components on a substrate by using a board level shield having virtual grounding capability. Further exemplary embodiments are disclosed of methods relating to making system in package (SiP) or system on chip (SoC) shielded modules and methods relating to providing shielding for one or more components of SiP or SoC module.

5.

发明申请
CIRCUIT ASSEMBLIES WITH MULTIPLE INTERPOSER SUBSTRATES, AND METHODS OF FABRICATION 有权

公开(公告)号：US20160293534A1

公开(公告)日：2016-10-06

申请号：US15181872

申请日：2016-06-14

Applicant: Invensas Corporation

Inventor： Hong SHEN , Zhuowen Sun , Charles G. Woychik , Arkalgud Sitaram

IPC: H01L23/498 , H01L21/48 , H01L21/683 , H01L23/00 , H01L23/31 , H01L21/56 , H01L25/065 , H01L25/00

CPC classification number: H01L23/49833 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L21/561 , H01L21/6835 , H01L21/76898 , H01L23/3121 , H01L23/3128 , H01L23/498 , H01L23/49827 , H01L23/49838 , H01L23/538 , H01L23/5381 , H01L23/5383 , H01L23/5385 , H01L23/5389 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/97 , H01L25/03 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L2221/68327 , H01L2224/0401 , H01L2224/04042 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/81203 , H01L2224/81801 , H01L2224/92125 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2225/06589 , H01L2924/00014 , H01L2924/14 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/1615 , H01L2924/16153 , H01L2924/16251 , H01L2924/181 , H05K1/0271 , H05K1/111 , H05K1/141 , H05K1/181 , H01L2924/00012 , H01L2224/81 , H01L2224/85 , H01L2924/014 , H01L2224/83 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

6.

发明授权
Circuit assemblies with multiple interposer substrates, and methods of fabrication 有权
Title translation: 具有多个插入器基板的电路组件及其制造方法

公开(公告)号：US09402312B2

公开(公告)日：2016-07-26

申请号：US14275741

申请日：2014-05-12

Applicant: Invensas Corporation

Inventor： Hong Shen , Zhuowen Sun , Charles G. Woychik , Arkalgud Sitaram

IPC: H01L25/065 , H01L23/538 , H01L23/498 , H05K1/11 , H01L25/00 , H05K1/18 , H05K1/02 , H05K1/14

CPC classification number: H01L23/49833 , H01L21/4853 , H01L21/486 , H01L21/56 , H01L21/561 , H01L21/6835 , H01L21/76898 , H01L23/3121 , H01L23/3128 , H01L23/498 , H01L23/49827 , H01L23/49838 , H01L23/538 , H01L23/5381 , H01L23/5383 , H01L23/5385 , H01L23/5389 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/97 , H01L25/03 , H01L25/0652 , H01L25/0655 , H01L25/50 , H01L2221/68327 , H01L2224/0401 , H01L2224/04042 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/81203 , H01L2224/81801 , H01L2224/92125 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2225/06589 , H01L2924/00014 , H01L2924/14 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/1615 , H01L2924/16153 , H01L2924/16251 , H01L2924/181 , H05K1/0271 , H05K1/111 , H05K1/141 , H05K1/181 , H01L2924/00012 , H01L2224/81 , H01L2224/85 , H01L2924/014 , H01L2224/83 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

Abstract translation: 组合插入器（120）包括多个成分插入件（120.i），每个具有其自己的衬底（120.iS）并且在衬底的顶部和/或底部上具有电路层（例如再分配层）。顶层电路层可以是可以互连不同插入件的公共电路层（120R.T）的一部分。类似地，底部电路层可以是公共电路层（120R.B）的一部分。成分插入器基板（120.iS）最初是公共晶片的一部分，并且在将成分插入器基板与晶片分离之前制造公共顶层电路层。与使用单个大型基材相比，分离的基材的使用降低了应力。还提供其他功能。

7.

发明申请
System and Method for Bonding Package Lid 有权
Title translation: 用于粘合包装盖的系统和方法

公开(公告)号：US20150214128A1

公开(公告)日：2015-07-30

申请号：US14163000

申请日：2014-01-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Yen Lin , Yu-Chih Liu , Chin-Liang Chen , Wei-Ting Lin , Kuan-Lin Ho

IPC: H01L23/367 , H01L21/56 , H01L23/10

CPC classification number: H01L23/10 , H01L21/563 , H01L23/04 , H01L23/3142 , H01L23/3675 , H01L23/49816 , H01L23/49827 , H01L23/585 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L25/18 , H01L2224/03002 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/05572 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/06181 , H01L2224/11002 , H01L2224/131 , H01L2224/16145 , H01L2224/16147 , H01L2224/16225 , H01L2224/16237 , H01L2224/17181 , H01L2224/26145 , H01L2224/26175 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/83385 , H01L2224/92125 , H01L2224/92225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/06589 , H01L2924/00 , H01L2924/1432 , H01L2924/1434 , H01L2924/15311 , H01L2924/15788 , H01L2924/1579 , H01L2924/1615 , H01L2924/16152 , H01L2924/16235 , H01L2924/16251 , H01L2924/1631 , H01L2924/1632 , H01L2924/164 , H01L2924/014

Abstract: Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.

Abstract translation: 本文公开了一种具有包括工件的成形密封环的装置，所述工件包括设置在基板的第一侧上的至少一个电介质层，设置在所述至少一个电介质层中的密封环，以及至少一个凹槽密封环。盖子设置在工件上方，工件延伸到盖中的凹部中，并且第一热界面材料（TIM）接触密封环和盖子，第一TIM延伸到至少一个凹槽中。工件安装到包装托架上。模具安装在工件的第一侧上并设置在凹部中。第一底部填充物设置在模具下方，第二底部填充物设置在工件和包装载体之间。第一TIM置于第一底部填充物和第二底部填充物之间。