公开(公告)号：US20240063079A1

公开(公告)日：2024-02-22

申请号：US17891218

申请日：2022-08-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tung-Liang Shao ,  Yu-Sheng Huang ,  Kuo Yang Wu ,  Chen-Hua Yu

IPC分类号： H01L23/367 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/44 ,  H01L23/373 ,  H01L25/065

CPC分类号： H01L23/3675 ,  H01L24/32 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/73 ,  H01L23/49838 ,  H01L21/4882 ,  H01L23/3677 ,  H01L23/44 ,  H01L23/3735 ,  H01L24/08 ,  H01L25/0655 ,  H01L24/29 ,  H01L2224/08235 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2924/3511 ,  H01L2924/182 ,  H01L2924/16196 ,  H01L2924/16235 ,  H01L2924/1632 ,  H01L2924/16587 ,  H01L2224/29187

摘要： In an embodiment, a package is provided. The package includes a semiconductor device; an encapsulant laterally surrounding the semiconductor device; and a heat dissipation structure disposed over the semiconductor device and the encapsulant, wherein the heat dissipation structure includes a plurality of pillars and a porous layer extending over sidewalls of the plurality of pillars.

公开(公告)号：US11806903B2

公开(公告)日：2023-11-07

申请号：US17391720

申请日：2021-08-02

申请人： Mitsubishi Electric Corporation

发明人： Hiroyuki Masumoto

IPC分类号： B29C45/14 ,  H01L21/48 ,  H01L23/04 ,  H01L23/049 ,  H01L23/373 ,  H01L23/00 ,  H01L25/07 ,  B29L31/34

CPC分类号： B29C45/14426 ,  B29C45/14065 ,  H01L21/4817 ,  H01L23/049 ,  H01L23/3735 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/072 ,  B29L2031/3406 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2924/1306 ,  H01L2924/13055 ,  H01L2924/15787 ,  H01L2924/1616 ,  H01L2924/1632

摘要： Each of a plurality of terminals has a first portion and a second portion being a connection target for a semiconductor element. A manufacturing method of a housing includes a first step arranging, for a lower mold provided with a plurality of holes each of which is a target into which the first portion is inserted, a nest having a third portion covering at least one of the holes, a second step arranging, for the lower mold with the nest being arranged therein, the plurality of terminals by inserting the first portion into the hole not covered by the third portion, a third step arranging an upper mold on the lower mold with the nest and the plurality of terminals being arranged therein, and a fourth step, which is executed after the third step, obtaining the housing by performing resin molding using the lower mold and the upper mold.

公开(公告)号：US20230317539A1

公开(公告)日：2023-10-05

申请号：US17986995

申请日：2022-11-15

申请人： Samsung Electronics Co., Ltd.

发明人： Bo In NOH ,  Jeong Hoon AHN ,  Yun Ki CHOI

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/3135 ,  H01L23/49833 ,  H01L24/32 ,  H01L24/16 ,  H01L24/73 ,  H01L23/315 ,  H01L23/49822 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2924/3511 ,  H01L2224/73204 ,  H01L2224/16014 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2924/1616 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/183 ,  H01L2924/186 ,  H01L2224/3201 ,  H01L2224/32055 ,  H01L2224/32053 ,  H01L2224/32059 ,  H01L23/49816 ,  H01L25/0655

摘要： A semiconductor package includes a circuit board, an interposer structure on the circuit board, a first semiconductor chip and a second semiconductor chip on the interposer structure, the first and the second semiconductor chips electrically connected to the interposer structure and spaced apart from each other, and a mold layer between the first and second semiconductor chips, the mold layer separating the first and second semiconductor chips. A slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and an angle defined by a bottom side of the mold layer and the side wall of the mold layer is less than or equal to ninety degrees.

公开(公告)号：US20230147273A1

公开(公告)日：2023-05-11

申请号：US17821920

申请日：2022-08-24

申请人： Apple Inc.

发明人： Brett W. Degner ,  Jie-Hua Zhao ,  Kristopher P. Laurent ,  Michael E. Leclerc ,  Rangaraj Dhanasekaran ,  Simon J. Trivett

IPC分类号： H01L23/00 ,  H01L25/16 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01L23/562 ,  H01L25/16 ,  H01L25/0655 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/49816 ,  H01L21/4817 ,  H01L21/4853 ,  H01L24/81 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2224/73253 ,  H01L2224/32245 ,  H01L2224/16225 ,  H01L2224/81097 ,  H01L2924/1616 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/1659

摘要： Electronic assemblies and methods of assembly are described. In an embodiment, an electronic assembly includes a stiffener structure shear bonded to an opposite side of a module substrate from a ball grid array (BGA) package. The stiffener structure may be shear bonded at elevated temperature after bonding of the BGA package to lock in a flat or near-flat surface contour of the module substrate.

公开(公告)号：US20180082913A1

公开(公告)日：2018-03-22

申请号：US15823744

申请日：2017-11-28

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Yu-Te HSIEH

IPC分类号： H01L23/10 ,  H01L23/00 ,  H01L21/302 ,  H01L23/31 ,  H01L23/498 ,  H01L23/48

CPC分类号： H01L23/10 ,  H01L21/302 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/525 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L29/0657 ,  H01L2224/29021 ,  H01L2224/29022 ,  H01L2224/29034 ,  H01L2224/29099 ,  H01L2224/32013 ,  H01L2224/32111 ,  H01L2224/32112 ,  H01L2224/32237 ,  H01L2224/32238 ,  H01L2224/325 ,  H01L2224/83193 ,  H01L2224/83856 ,  H01L2924/00014 ,  H01L2924/16235 ,  H01L2924/1632 ,  H01L2924/1659 ,  H01L2924/16788 ,  H01L2224/13099

摘要： Implementations of semiconductor packages may include: a semiconductor wafer, a glass lid fixedly coupled to a first side of the semiconductor die by an adhesive, a redistribution layer coupled to a second side of the semiconductor die, and a plurality of ball mounts coupled to the redistribution layer on a side of the redistribution layer coupled to the semiconductor die. The adhesive may be located in a trench around a perimeter of the semiconductor die and located in a corresponding trench around a perimeter of the glass lid.

公开(公告)号：US09673119B2

公开(公告)日：2017-06-06

申请号：US14163000

申请日：2014-01-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Yen Lin ,  Yu-Chih Liu ,  Chin-Liang Chen ,  Wei-Ting Lin ,  Kuan-Lin Ho

IPC分类号： H01L23/34 ,  H01L23/10 ,  H01L23/04 ,  H01L23/31 ,  H01L21/56 ,  H01L23/58 ,  H01L23/367 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/498

CPC分类号： H01L23/10 ,  H01L21/563 ,  H01L23/04 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/1615 ,  H01L2924/16152 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1631 ,  H01L2924/1632 ,  H01L2924/164 ,  H01L2924/014

摘要： Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.

公开(公告)号：US20170018510A1

公开(公告)日：2017-01-19

申请号：US15280175

申请日：2016-09-29

申请人： Invensas Corporation

发明人： Hong SHEN ,  Liang WANG ,  Rajesh KATKAR ,  Charles G. WOYCHIK ,  Guilian GAO

IPC分类号： H01L23/00 ,  H01L23/053 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48

CPC分类号： H01L23/562 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L23/053 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/16153 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/16315 ,  H01L2924/1632 ,  H01L2924/167 ,  H01L2924/16787 ,  H01L2924/16788 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/01029 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： Die (110) are attached to an interposer (420), and the interposer/die assembly is placed into a lid cavity (510). The lid (210) is attached to the top of the assembly, possibly to the encapsulant (474) at the top. The lid's legs (520) surround the cavity and extend down below the top surface of the interposer's substrate (420S), possibly to the level of the bottom surface of the substrate or lower. The legs (520) may or may not be attached to the interposer/die assembly. In fabrication, the interposer wafer (420SW) has trenches (478) which receive the lid's legs during the lid placement. The interposer wafer is later thinned to remove the interposer wafer portion below the legs and to dice the interposer wafer. The thinning process also exposes, on the bottom, conductive vias (450) passing through the interposer substrate. Other features are also provided.

摘要翻译： 模具（110）附接到插入件（420），并且插入器/模具组件被放置在盖腔（510）中。 盖（210）附接到组件的顶部，可能附接到顶部的密封剂（474）。 盖的腿（520）围绕空腔并且向下延伸到插入器的衬底（420S）的顶表面下方，可能地到衬底的底表面的高度或更低。 腿（520）可以或可以不附接到插入件/模具组件。 在制造中，插入器晶片（420SW）具有在盖放置期间接收盖的腿的沟槽（478）。 中间层晶片稍后变薄以去除腿下方的插入片晶片部分并且切割插入片晶片。 薄化工艺还在底部暴露穿过内插衬底的导电通孔（450）。 还提供其他功能。

公开(公告)号：US20160343687A1

公开(公告)日：2016-11-24

申请号：US14716176

申请日：2015-05-19

申请人： Micron Technology, Inc.

发明人： Sameer S. Vadhavkar ,  Jaspreet S. Gandhi ,  James M. Derderian

IPC分类号： H01L25/065 ,  H01L23/373 ,  H01L21/78 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/78 ,  H01L23/3675 ,  H01L23/373 ,  H01L23/3738 ,  H01L23/4012 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92242 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/167 ,  H01L2224/83

摘要： Semiconductor device assemblies with heat transfer structures formed from semiconductor materials are disclosed herein. In one embodiment, a semiconductor device assembly can include a thermal transfer structure formed from a semiconductor substrate. The thermal transfer structure includes an inner region, an outer region projecting from the inner region, and a cavity defined in the outer region by the inner and outer regions. The semiconductor device assembly further includes a stack of first semiconductor dies in the cavity, and a second semiconductor die attached to the outer region of the thermal transfer structure and enclosing the stack of first semiconductor dies within the cavity.

摘要翻译： 本文公开了具有由半导体材料形成的传热结构的半导体器件组件。 在一个实施例中，半导体器件组件可以包括由半导体衬底形成的热传递结构。 热转印结构包括内部区域，从内部区域突出的外部区域和由内部区域和外部区域限定在外部区域中的空腔。 半导体器件组件还包括在空腔中的第一半导体管芯堆叠，以及附接到热传递结构的外部区域并且在空腔内封装第一半导体管芯堆叠的第二半导体管芯。

公开(公告)号：US09478504B1

公开(公告)日：2016-10-25

申请号：US14745237

申请日：2015-06-19

申请人： Invensas Corporation

发明人： Hong Shen ,  Liang Wang ,  Rajesh Katkar ,  Charles G. Woychik ,  Guilian Gao

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/053 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L23/053 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/16153 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/16315 ,  H01L2924/1632 ,  H01L2924/167 ,  H01L2924/16787 ,  H01L2924/16788 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/01029 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： Die (110) are attached to an interposer (420), and the interposer/die assembly is placed into a lid cavity (510). The lid (210) is attached to the top of the assembly, possibly to the encapsulant (474) at the top. The lid's legs (520) surround the cavity and extend down below the top surface of the interposer's substrate (420S), possibly to the level of the bottom surface of the substrate or lower. The legs (520) may or may not be attached to the interposer/die assembly. In fabrication, the interposer wafer (420SW) has trenches (478) which receive the lid's legs during the lid placement. The interposer wafer is later thinned to remove the interposer wafer portion below the legs and to dice the interposer wafer. The thinning process also exposes, on the bottom, conductive vias (450) passing through the interposer substrate. Other features are also provided.

摘要翻译： 模具（110）附接到插入件（420），并且插入器/模具组件被放置在盖腔（510）中。 盖（210）附接到组件的顶部，可能附接到顶部的密封剂（474）。 盖的腿（520）围绕空腔并且向下延伸到插入器的衬底（420S）的顶表面下方，可能地到衬底的底表面的高度或更低。 腿（520）可以或可以不附接到插入件/模具组件。 在制造中，插入器晶片（420SW）具有在盖放置期间接收盖的腿的沟槽（478）。 中间层晶片稍后变薄以去除腿下方的插入片晶片部分并且切割插入片晶片。 薄化工艺还在底部暴露穿过内插衬底的导电通孔（450）。 还提供其他功能。

公开(公告)号：US06576999B2

公开(公告)日：2003-06-10

申请号：US09863130

申请日：2001-05-23

申请人： Norio Sakai ,  Kazuhiro Iida

发明人： Norio Sakai ,  Kazuhiro Iida

IPC分类号： H01L2304

CPC分类号： H05K3/403 ,  H01L23/49805 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/142 ,  H01L2924/15159 ,  H01L2924/15162 ,  H01L2924/15313 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H05K1/0306 ,  H05K3/0052 ,  H05K3/3442 ,  H05K3/4061 ,  H05K2201/09181 ,  H01L2224/0401

摘要： A method for manufacturing an electronic component includes forming an aggregate electronic component including a plurality of electronic components and dividing the aggregate electronic component to separate the plurality of electronic components to form individual electronic components. Through-holes are formed in a laminated body providing an aggregate electronic component wherein via-hole conductors are arranged so as not pass through the aggregate electronic component in a thickness direction thereof, the via-hole conductors are divided by the through-holes, and each divided portion provides an external terminal electrode. Then, by dividing the laminated body along the dividing lines passing through the through-holes, a plurality of individual electronic components are produced.

摘要翻译： 一种电子部件的制造方法，其特征在于，形成包含多个电子部件的集合电子部件，并分割所述集合电子部件，分离所述多个电子部件，形成各个电子部件。 通孔形成在提供聚集电子部件的层叠体中，其中通孔导体布置成不沿其厚度方向通过聚集电子部件，通孔导体被通孔分隔，并且 每个分割部分提供外部端子电极。 然后，通过沿着通过通孔的分割线分割层叠体，制造多个单独的电子部件。