公开(公告)号：US20240118141A1

公开(公告)日：2024-04-11

申请号：US18391769

申请日：2023-12-21

Applicant: PixArt Imaging Incorporation

Inventor： Chih-Ming Sun ,  Ming-Han Tsai

IPC: G01J5/02 ,  A61B5/00 ,  A61B5/01 ,  B81B7/00 ,  B81B7/02 ,  G01J5/00 ,  G01J5/04 ,  G01J5/14 ,  G01K13/20 ,  H04N23/56

CPC classification number: G01J5/0265 ,  A61B5/01 ,  A61B5/681 ,  B81B7/0025 ,  B81B7/0061 ,  B81B7/02 ,  G01J5/0025 ,  G01J5/027 ,  G01J5/04 ,  G01J5/046 ,  G01J5/14 ,  G01K13/20 ,  H04N23/56 ,  A61B5/02416 ,  B81B2201/0214 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0278 ,  H01L2224/48091 ,  H01L2924/16151 ,  H01L2924/16153 ,  H01L2924/16235

Abstract: The present invention discloses a wearable device with combined sensing capabilities, which includes a wearable assembly and at least one multi-function sensor module. The wearable assembly is suitable to be worn on apart of a user's body. The wearable assembly includes at least one light-transmissible window. The multi-function sensor module is located inside the wearable assembly, for performing an image sensing function and an infrared temperature sensing function. The multi-function sensor module includes an image sensor module for sensing a physical or a biological feature of an object through the light-transmissible window by way of image sensing; and an infrared temperature sensor module for sensing temperature through the light-transmissible window by way of infrared temperature sensing.

公开(公告)号：US20230378007A1

公开(公告)日：2023-11-23

申请号：US17750428

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Yu-Sheng Lin ,  Shu-Shen Yeh ,  Chien-Shen Chen ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Ming-Chih Yew ,  Chin-Hua Wang ,  Po-Chen Lai ,  Chia-Kuei Hsu

IPC: H01L23/055 ,  H01L25/065 ,  H01L23/10 ,  H01L21/48

CPC classification number: H01L23/055 ,  H01L25/0655 ,  H01L23/10 ,  H01L21/4871 ,  H01L2924/35121 ,  H01L2924/1611 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/1631 ,  H01L2924/1811 ,  H01L2924/182 ,  H01L24/73

Abstract: A package assembly includes a package substrate, an interposer module on the package substrate, and a package lid on the interposer module and attached to the package substrate. The package lid includes an outer lid including an outer lid material and including an outer lid plate portion. The package lid further includes an inner lid including an inner lid material different than the outer lid material and including an inner lid plate portion attached to a bottom surface of the outer lid plate portion.

公开(公告)号：US09905507B2

公开(公告)日：2018-02-27

申请号：US15181872

申请日：2016-06-14

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Zhuowen Sun ,  Charles G. Woychik ,  Arkalgud Sitaram

IPC: H01L21/768 ,  H01L23/498 ,  H05K1/11 ,  H01L25/00 ,  H05K1/18 ,  H05K1/02 ,  H05K1/14 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/683 ,  H01L25/03 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1615 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/111 ,  H05K1/141 ,  H05K1/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

公开(公告)号：US20170345732A1

公开(公告)日：2017-11-30

申请号：US15676963

申请日：2017-08-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wensen Hung ,  Szu-Po Huang ,  Hsiang-Fan Lee ,  Kim Hong Chen ,  Chi-Hsi Wu ,  Shin-Puu Jeng

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/42 ,  H01L23/498 ,  H01L23/04 ,  H01L23/10 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/36 ,  H01L23/04 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/33519 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/1679 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/014

Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

公开(公告)号：US09831302B2

公开(公告)日：2017-11-28

申请号：US15360121

申请日：2016-11-23

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Hong Shen ,  Rajesh Katkar

IPC: H01L21/02 ,  H01L49/02 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/11 ,  H01L25/16 ,  H01L25/00 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/11 ,  H01L25/115 ,  H01L25/165 ,  H01L25/50 ,  H01L28/40 ,  H01L28/65 ,  H01L2224/05009 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1205 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/00

Abstract: A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

公开(公告)号：US09716049B2

公开(公告)日：2017-07-25

申请号：US14813592

申请日：2015-07-30

Applicant: Socionext Inc.

Inventor： Kazuyuki Urago ,  Nobutaka Shimizu

IPC: H01L23/053 ,  H01L23/498 ,  H01L21/52 ,  H01L23/04 ,  H01L23/10 ,  H01L23/552 ,  H01L23/00

CPC classification number: H01L23/053 ,  H01L21/52 ,  H01L23/04 ,  H01L23/10 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/16153 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1631 ,  H01L2924/16315 ,  H01L2924/1659 ,  H01L2924/16724 ,  H01L2924/16747 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor device includes: a substrate; a semiconductor element disposed on the substrate; a plurality of electrodes disposed on the substrate separately from one another and arranged so as to surround the semiconductor element in a plan view; a lid that cover the semiconductor element, the lid including an inner portion and a periphery portion that is outer than the inner portion in a plan view, the lid including a plurality of first protruding members that is provided separately from one another, the first protruding members being disposed in the inner portion; and conductive members disposed between the plurality of electrodes and the plurality of protruding members disposed in positions opposed to the plurality of electrodes respectively, the conductive members being joined to the plurality of electrodes and the plurality of protruding members respectively.

公开(公告)号：US09640518B2

公开(公告)日：2017-05-02

申请号：US15067203

申请日：2016-03-11

Applicant: BRIDGE SEMICONDUCTOR CORPORATION

Inventor： Charles W. C. Lin ,  Chia-Chung Wang

IPC: H01L23/34 ,  H01L25/10 ,  H01L23/36 ,  H01L23/00 ,  H01L25/00 ,  H01L23/367 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2225/1094 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/1531 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/15793 ,  H01L2924/16153 ,  H01L2924/16172 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/16724 ,  H01L2924/16747 ,  H01L2924/1676 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred embodiment, the method is characterized by forming through openings that extend through a metallic carrier between first and second surfaces of the metallic carrier, attaching a chip-on-interposer subassembly on the metallic carrier using an adhesive, with the chip inserted into a cavity of the metallic carrier, and with the chip-on-interposer subassembly attached to the metallic carrier, forming first and second buildup circuitry on a first surface of the interposer and the second surface of the metallic carrier, respectively, and subsequently forming plated through holes that extend into the through openings to provide electrical and thermal connections between the first and second buildup circuitry. The method and resulting device advantageously provides vertical signal routing and stacking capability for a semiconductor package.

公开(公告)号：US20160345106A1

公开(公告)日：2016-11-24

申请号：US15111224

申请日：2014-12-04

Applicant: EPCOS AG

Inventor： Wolfgang Pahl ,  Gregor Feiertag

IPC: H04R19/04 ,  H04R19/00 ,  H04R1/40 ,  B81B7/00 ,  H04R1/04

CPC classification number: H04R19/04 ,  B81B7/0061 ,  B81B2201/0257 ,  B81B2207/012 ,  B81B2207/07 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2924/10158 ,  H01L2924/15192 ,  H01L2924/16153 ,  H04R1/04 ,  H04R1/406 ,  H04R5/027 ,  H04R19/005 ,  H04R2201/003 ,  H04R2410/03 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A multi-MEMS module is specified which can be produced expediently and enables a smaller design. The module comprises a housing having an interior and a first and a second opening, a first MEMS chip and a second MEMS chip. The first MEMS chip is acoustically coupled to the first opening. The second MEMS chip is acoustically coupled to the second opening.

Abstract translation: 指定了可以方便生产并实现更小设计的多MEMS模块。 模块包括具有内部和第一和第二开口的壳体，第一MEMS芯片和第二MEMS芯片。 第一个MEMS芯片声耦合到第一个开口。 第二MEMS芯片声耦合到第二开口。

公开(公告)号：US20160293534A1

公开(公告)日：2016-10-06

申请号：US15181872

申请日：2016-06-14

Applicant: Invensas Corporation

Inventor： Hong SHEN ,  Zhuowen Sun ,  Charles G. Woychik ,  Arkalgud Sitaram

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1615 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/111 ,  H05K1/141 ,  H05K1/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

公开(公告)号：US20160260644A1

公开(公告)日：2016-09-08

申请号：US14998324

申请日：2015-12-24

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Lung-Shan Chuang ,  Ching-Wen Chiang ,  Tzung-Yen Wu ,  Chun-Hung Lu

IPC: H01L23/053 ,  H01L23/31 ,  H01L21/78 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/06 ,  H01L23/498

CPC classification number: H01L23/053 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/167 ,  H01L2224/83 ,  H01L2224/81

Abstract: An electronic package is provided, including a circuit portion, an electronic element disposed on the circuit portion and a lid member disposed on the circuit portion to cover the electronic element. A separation portion is formed between the lid member and the electronic element. The lid member facilitates to prevent warping of the overall package structure. The invention further provides a method for fabricating the electronic package.

Abstract translation: 提供一种电子封装，包括电路部分，设置在电路部分上的电子元件和设置在电路部分上以覆盖电子元件的盖子部件。 在盖构件和电子元件之间形成分离部。 盖构件有助于防止整个包装结构的翘曲。 本发明还提供一种制造电子封装的方法。