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公开(公告)号：US20200027809A1
公开(公告)日：2020-01-23
申请号：US16587463
申请日：2019-09-30
Inventor： Wensen Hung , Szu-Po Huang , Hsiang-Fan Lee , Kim Hong Chen , Chi-Hsi Wu , Shin-Puu Jeng
IPC: H01L23/36 , H01L23/04 , H01L23/10 , H01L25/065 , H01L23/367 , H01L23/42 , H01L23/498
Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.
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公开(公告)号：US20190096781A1
公开(公告)日：2019-03-28
申请号：US16206903
申请日：2018-11-30
Inventor： Wensen Hung , Szu-Po Huang , Hsiang-Fan Lee , Kim Hong Chen , Chi-Hsi Wu , Shin-Puu Jeng
IPC: H01L23/36 , H01L23/498 , H01L25/065 , H01L23/367 , H01L23/04 , H01L23/42 , H01L23/10 , H01L25/18 , H01L23/00
CPC classification number: H01L23/36 , H01L23/04 , H01L23/10 , H01L23/3675 , H01L23/3677 , H01L23/42 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/92 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/13025 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/29011 , H01L2224/291 , H01L2224/2919 , H01L2224/29294 , H01L2224/29339 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/33519 , H01L2224/73204 , H01L2224/73253 , H01L2224/81815 , H01L2224/83191 , H01L2224/92125 , H01L2224/92225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/06589 , H01L2924/1431 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/15311 , H01L2924/16153 , H01L2924/16251 , H01L2924/1679 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00 , H01L2924/014
Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.
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公开(公告)号：US09735082B2
公开(公告)日：2017-08-15
申请号：US14096952
申请日：2013-12-04
Inventor： Wensen Hung , Szu-Po Huang , Hsiang-Fan Lee , Kim Hong Chen , Chi-Hsi Wu , Shin-Puu Jeng
IPC: H01L23/544 , H01L23/36 , H01L23/04 , H01L23/10 , H01L25/065 , H01L23/367 , H01L23/42 , H01L23/00 , H01L25/18 , H01L23/498
CPC classification number: H01L23/36 , H01L23/04 , H01L23/10 , H01L23/3675 , H01L23/3677 , H01L23/42 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/83 , H01L24/92 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/13025 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/29011 , H01L2224/291 , H01L2224/2919 , H01L2224/29294 , H01L2224/29339 , H01L2224/32225 , H01L2224/32245 , H01L2224/33181 , H01L2224/33519 , H01L2224/73204 , H01L2224/73253 , H01L2224/81815 , H01L2224/83191 , H01L2224/92125 , H01L2224/92225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/06589 , H01L2924/1431 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/15311 , H01L2924/16153 , H01L2924/16251 , H01L2924/1679 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/00 , H01L2924/014
Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.
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公开(公告)号：US20160111350A1
公开(公告)日：2016-04-21
申请号：US14981001
申请日：2015-12-28
Inventor： Kim Hong Chen , Szu-Po Huang , Shin-Puu Jeng , Wensen Hung
IPC: H01L23/473 , B23P15/26
CPC classification number: H01L23/473 , B23P15/26 , H01L23/44 , H01L23/46 , H01L33/648 , H01L2224/73253 , Y10T29/49117
Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of cooling packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a substrate including a semiconductor device mounting region, a cover coupled to a perimeter of the substrate, and members disposed between the substrate and the cover. The package includes partitions, with each partition being disposed between two adjacent members. The package includes a fluid inlet port coupled to the cover, and a fluid outlet port coupled to one of the partitions.
Abstract translation: 公开了用于半导体器件，封装半导体器件的封装以及冷却封装的半导体器件的方法。 在一些实施例中，用于半导体器件的封装包括：衬底，其包括半导体器件安装区域，耦合到衬底的周边的覆盖物以及设置在衬底和覆盖物之间的部件。 该包装包括分隔件，每个分隔件设置在两个相邻构件之间。 所述包装包括连接到所述盖的流体入口端口和连接到所述隔板中的一个的流体出口。
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5.发明授权Packages for semiconductor devices, packaged semiconductor devices, and methods of cooling packaged semiconductor devices 有权用于半导体器件，封装半导体器件的封装以及冷却封装的半导体器件的方法公开(公告)号：US09224673B2
公开(公告)日：2015-12-29
申请号：US13791077
申请日：2013-03-08
Inventor： Kim Hong Chen , Wensen Hung , Szu-Po Huang , Shin-Puu Jeng
IPC: H01L23/473 , H01L33/64 , H01L23/46 , H01L23/44
CPC classification number: H01L23/473 , B23P15/26 , H01L23/44 , H01L23/46 , H01L33/648 , H01L2224/73253 , Y10T29/49117
Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of cooling packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a substrate including a semiconductor device mounting region, a cover coupled to a perimeter of the substrate, and members disposed between the substrate and the cover. The package includes partitions, with each partition being disposed between two adjacent members. The package includes a fluid inlet port coupled to the cover, and a fluid outlet port coupled to one of the partitions.
Abstract translation: 公开了用于半导体器件，封装半导体器件的封装以及冷却封装的半导体器件的方法。 在一些实施例中，用于半导体器件的封装包括：衬底，其包括半导体器件安装区域，耦合到衬底的周边的覆盖物以及设置在衬底和覆盖物之间的部件。 该包装包括分隔件，每个分隔件设置在两个相邻构件之间。 所述包装包括连接到所述盖的流体入口端口和连接到所述隔板中的一个的流体出口。
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Patent Agency Ranking
公开(公告)号：US09076754B2
公开(公告)日：2015-07-07
申请号：US14144691
申请日：2013-12-31
Inventor： Wensen Hung , Szu-Po Huang , Kim Hong Chen , Shin-Puu Jeng
IPC: H01L23/10 , H01L23/367 , H01L23/34
CPC classification number: H01L23/3672 , H01L23/055 , H01L23/10 , H01L23/34 , H01L23/36 , H01L23/3675 , H01L23/42 , H01L23/49816 , H01L25/0657 , H01L25/18 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/15311
Abstract: A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion extending beyond edges of the first die. A first Thermal Interface Material (TIM) is overlying and contacting a top surface of the first die. A heat sink has a first bottom surface over and contacting the first TIM. A second TIM is overlying and contacting the second portion of the second die. A heat dissipating ring is overlying and contacting the second TIM.
Abstract translation: 包装包括第一管芯和第一管芯下面的第一管芯和与第一管芯相同的第一管芯堆叠。 第二模具包括由第一模具重叠的第一部分和延伸超过第一模具的边缘的第二部分。 第一个热界面材料（TIM）覆盖并接触第一个模具的顶面。 散热器具有第一底表面并接触第一TIM。 第二TIM覆盖并接触第二模具的第二部分。 散热环已经覆盖并与第二个TIM接触。
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公开(公告)号：US08946887B1
公开(公告)日：2015-02-03
申请号：US13957727
申请日：2013-08-02
Inventor： Wensen Hung , Szu-Po Huang , Kim Hong Chen , Shin-Puu Jeng
Abstract: A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion not overlapped by the first die. A first Thermal Interface Material (TIM) is over and contacting a top surface of the first die. A heat dissipating lid has a first bottom surface contacting the first TIM. A second TIM is over and contacting the second portion of the second die. A heat dissipating ring is over and contacting the second TIM.
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公开(公告)号：US11587886B2
公开(公告)日：2023-02-21
申请号：US16854666
申请日：2020-04-21
Inventor： Kuan-Yu Huang , Sung-Hui Huang , Pai-Yuan Li , Shu-Chia Hsu , Hsiang-Fan Lee , Szu-Po Huang
Abstract: A semiconductor device includes a substrate, an electronic component, a ring structure and an adhesive layer. The substrate has a first surface. The electronic component is over the first surface of the substrate. The ring structure is over the first surface of the substrate, wherein the ring structure includes a first part having a first height, and a second part recessed from the bottom surface and having a second height lower than the first height. The adhesive layer is interposed between the first part of the ring structure and the substrate, and between the second part of the ring structure and the substrate.
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公开(公告)号：US10446520B2
公开(公告)日：2019-10-15
申请号：US15722983
申请日：2017-10-02
Inventor： Shin-Puu Jeng , Shang-Yun Hou , Kim Hong Chen , Wensen Hung , Szu-Po Huang
IPC: H01L25/065 , H01L23/00 , H01L23/13 , H01L23/498 , H01L25/00 , H01L23/31 , H01L23/538 , H01L21/683 , H01L25/18 , H01L21/56 , H01L21/48 , H01L23/367 , H01L23/42
Abstract: Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects.
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公开(公告)号：US09985001B2
公开(公告)日：2018-05-29
申请号：US15350292
申请日：2016-11-14
Inventor： Kim Hong Chen , Szu-Po Huang , Shin-Puu Jeng , Wensen Hung
IPC: H01L21/768 , H01L21/56 , H01L23/00 , H01L23/31 , H01L23/522 , H01L25/065 , H01L23/498 , H01L21/48 , H01L23/538 , H01L21/288 , H01L21/3105 , H01L21/683 , H01L25/10 , H01L25/11 , H01L25/03 , H01L25/00 , H01L25/07
CPC classification number: H01L25/0657 , H01L21/288 , H01L21/31053 , H01L21/486 , H01L21/56 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L21/76802 , H01L21/76837 , H01L21/76877 , H01L23/3114 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L23/49822 , H01L23/522 , H01L23/5226 , H01L23/5384 , H01L23/5389 , H01L24/11 , H01L24/19 , H01L24/20 , H01L24/81 , H01L24/83 , H01L24/97 , H01L25/00 , H01L25/03 , H01L25/065 , H01L25/0652 , H01L25/0655 , H01L25/074 , H01L25/105 , H01L25/117 , H01L25/50 , H01L2221/68359 , H01L2224/0231 , H01L2224/04105 , H01L2224/12105 , H01L2224/13025 , H01L2224/13082 , H01L2224/13083 , H01L2224/16105 , H01L2224/16145 , H01L2224/16148 , H01L2224/16225 , H01L2224/16235 , H01L2224/73204 , H01L2224/81005 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L2224/83005 , H01L2224/838 , H01L2224/9202 , H01L2224/94 , H01L2224/96 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06548 , H01L2924/15311 , H01L2224/81 , H01L2224/82 , H01L2224/83 , H01L2224/19 , H01L2224/11 , H01L2924/00014 , H01L2224/214
Abstract: A package includes a first molding material, a first device die molded in the molding material, a Through Via (TV) penetrating through the first molding material, and a redistribution line over the first molding material. The redistribution line is electrically connected to the TV. A second device die is over and bonded to the first device die through flip-chip bonding. A second molding material molds the second device die therein.
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