公开(公告)号：US12015009B2

公开(公告)日：2024-06-18

申请号：US18080610

申请日：2022-12-13

申请人： Intel Corporation

发明人： Edward Burton

IPC分类号： H01L25/00 ,  H01L23/00

CPC分类号： H01L25/00 ,  H01L24/16 ,  H01L2224/16145

摘要： Stacked semiconductor die architectures having one or more base dies and techniques of forming such architectures are described. The stacked semiconductor die architectures may be included in or used to form semiconductor packages. A stacked semiconductor die architecture can include: (i) one or more base dies (e.g., at least one disaggregated base die, at least one monolithic base die, etc.); and (ii) a carrier wafer having multiple stacked semiconductor dies embedded in the carrier wafer, where the carrier wafer is on the one or more base dies and where one or more interconnect structures (e.g., wires, bumps, microbumps, pillars, etc.) couple the one or more base dies to the carrier wafer and/or the stacked semiconductor dies.

公开(公告)号：US11923328B2

公开(公告)日：2024-03-05

申请号：US17522825

申请日：2021-11-09

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Hsin He Huang

IPC分类号： H01L23/00 ,  H01L21/304 ,  H01L21/683 ,  H01L23/538 ,  H01L25/00

CPC分类号： H01L24/14 ,  H01L21/304 ,  H01L21/6838 ,  H01L23/5389 ,  H01L25/00 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14515

摘要： A semiconductor device includes a semiconductor die having a first surface and a second surface opposite to the first surface, a plurality of first real conductive pillars in a first region on the first surface, and a plurality of supporters in a second region adjacent to the first region. An area density of the plurality of supporters in the second region is in a range of from about 50% to about 100% to an area density of the plurality of first real conductive pillars in the first region. A method for manufacturing a semiconductor package including the semiconductor device is also disclosed in the present disclosure.

公开(公告)号：US11764172B2

公开(公告)日：2023-09-19

申请号：US17586940

申请日：2022-01-28

申请人： Murata Manufacturing Co., Ltd.

发明人： Hiroshi Nishikawa

IPC分类号： H03F3/14 ,  H03F1/56 ,  H03F3/191 ,  H03G3/20 ,  H03G5/16 ,  H01L23/66 ,  H04B1/40 ,  H01L25/00 ,  H01P1/15 ,  H01L25/16

CPC分类号： H01L23/66 ,  H01L25/00 ,  H01P1/15 ,  H04B1/40 ,  H01L25/16 ,  H01L2223/6644 ,  H01L2223/6661

摘要： An integrated circuit (IC) includes a first switch, a second switch, an amplifier electrically connected between the first switch and the second switch, and a base. The first switch, the second switch, and the amplifier are provided on the base. In a top view of the base, the amplifier is disposed between the first switch and the second switch.

公开(公告)号：US11676944B2

公开(公告)日：2023-06-13

申请号：US17246982

申请日：2021-05-03

申请人： Intel Corporation

发明人： Junfeng Zhao

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/50 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L24/19 ,  H01L24/96 ,  H01L25/00 ,  H01L25/50 ,  H01L21/50 ,  H01L21/565 ,  H01L23/49816 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73217 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2924/00012

摘要： A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

公开(公告)号：US11675961B2

公开(公告)日：2023-06-13

申请号：US17670370

申请日：2022-02-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shun Li Chen ,  Li-Chun Tien ,  Ting Yu Chen ,  Wei-Ling Chang

IPC分类号： G06F30/398 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3947 ,  G06F30/3953 ,  G03F1/36 ,  H01L21/70 ,  H01L25/00 ,  H03K19/00

CPC分类号： G06F30/398 ,  G03F1/36 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3947 ,  G06F30/3953 ,  H01L21/70 ,  H01L25/00 ,  H03K19/00

摘要： A semiconductor cell structure includes four pairs of conductive segments, a first gate-strip, and a second gate-strip. A first conductive segment is configured to have a first supply voltage, and a second conductive segment is configured to have a second supply voltage. Each of the first gate-strip and the second gate-strip intersects an active zone over a channel region of a transistor. The first gate-strip is conductively connected to the second conductive segment. The semiconductor cell structure also includes a first dummy gate-strip and a second dummy gate-strip. The first dummy gate-strip separates from the first gate-strip by one CPP. The second dummy gate-strip separates from the second gate-strip by one CPP. The first gate-strip and the second gate-strip are separated from each other by two CPPs. The dummy gate-strip and the second dummy gate-strip are separated from each other by four CPPs.

公开(公告)号：US20190178458A1

公开(公告)日：2019-06-13

申请号：US16276082

申请日：2019-02-14

申请人： Hyundai Motor Company ,  Kia Motors Corporation

发明人： Chan Hee Kang

IPC分类号： F21S41/125 ,  F21S43/14 ,  F21S43/19 ,  F21S43/13 ,  H01L25/00 ,  F21S43/15 ,  F21S43/50

CPC分类号： F21S41/125 ,  B60Q2400/20 ,  F21K9/64 ,  F21S41/143 ,  F21S41/285 ,  F21S41/43 ,  F21S41/663 ,  F21S43/13 ,  F21S43/14 ,  F21S43/15 ,  F21S43/19 ,  F21S43/26 ,  F21S43/30 ,  F21S43/50 ,  F21S45/47 ,  F21Y2113/13 ,  F21Y2115/10 ,  H01L25/00

摘要： A light source module and a vehicle headlamp is provided. The light source module and the vehicle headlamp include a circuit board and first and second light emitting modules that are disposed on the circuit board. The first and second light emitting modules are divided by a partition wall. Each of the first and second light emitting modules includes a blue LED light source and a phosphor that is disposed on the blue LED light source. The phosphor is configured to be activated by the blue LED light source to emit first light and includes a phosphor film that is disposed on an exterior of the first light emitting module and the phosphor film is configured to emit a second light.

公开(公告)号：US20190137708A1

公开(公告)日：2019-05-09

申请号：US16180621

申请日：2018-11-05

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： Shozo OCHI ,  Daisuke SAKURAI

IPC分类号： G02B6/42

CPC分类号： G02B6/4274 ,  G02B6/4214 ,  G02B6/4268 ,  G02B6/4269 ,  H01L25/00

摘要： An optical module structure includes a main substrate, an interposer substrate electrically connected to the main substrate via a first protruding electrode, a first communication LSI electrically connected to the interposer substrate via a second protruding electrode, an IC element electrically connected to the interposer substrate via a lateral-surface connection terminal of the interposer substrate and via a third protruding electrode, an Si bench substrate electrically connected to the IC element via a fourth protruding electrode and via a lateral-surface connection terminal of the Si bench substrate, an optical element electrically connected to the Si bench substrate via a fifth protruding electrode, and an optical fiber optically connected via an optical waveguide formed on the Si bench substrate.

公开(公告)号：US20190113601A1

公开(公告)日：2019-04-18

申请号：US16218771

申请日：2018-12-13

申请人： Infineon Technologies AG

发明人： Saverio Trotta ,  Ashutosh Baheti ,  Ismail Nasr ,  Ngoc-Hoa Huynh ,  Martin Richard Niessner

IPC分类号： G01S7/03 ,  G01S13/00 ,  G01S13/34 ,  G01S13/87 ,  G01S7/35 ,  H01Q9/04 ,  G01S13/58 ,  G01S13/93 ,  G01S7/00 ,  H01Q19/30 ,  H01L23/66

CPC分类号： G01S7/032 ,  G01S7/006 ,  G01S7/038 ,  G01S7/354 ,  G01S13/003 ,  G01S13/343 ,  G01S13/584 ,  G01S13/87 ,  G01S13/931 ,  G01S2013/0245 ,  H01L23/66 ,  H01L25/00 ,  H01L2223/6677 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01Q9/0407 ,  H01Q19/30

摘要： In accordance with an embodiment, a packaged radio frequency (RF) circuit includes a radio frequency integrated circuit (RFIC) disposed on a substrate that has plurality of receiver circuits coupled to receive ports at a first edge of the RFIC, and a first transmit circuit coupled to a first transmit port at a second edge of the RFIC. The packaged RF circuit also includes a receive antenna system disposed on the package substrate adjacent to the first edge of the RFIC and a first transmit antenna disposed on the package substrate adjacent to the second edge of the RFIC and electrically coupled to the first transmit port of the RFIC. The receive antenna system includes a plurality of receive antenna elements that are each electrically coupled to a corresponding receive port.

公开(公告)号：US20190074284A1

公开(公告)日：2019-03-07

申请号：US16176634

申请日：2018-10-31

申请人： TOSHIBA MEMORY CORPORATION

发明人： Yoshihiro AKUTSU ,  Ryota KATSUMATA

IPC分类号： H01L27/11556 ,  H01L25/00 ,  H01L27/11573 ,  H01L27/1157 ,  H01L21/74 ,  H01L21/768 ,  H01L23/535 ,  H01L27/11582 ,  H01L27/11578

CPC分类号： H01L27/11556 ,  H01L21/743 ,  H01L21/76889 ,  H01L23/535 ,  H01L25/00 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of theNAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

公开(公告)号：US20180308616A1

公开(公告)日：2018-10-25

申请号：US16022055

申请日：2018-06-28

申请人： Huawei Technologies Co., Ltd.

发明人： Yuping GONG ,  Zhaozheng HOU ,  Junhe WANG

IPC分类号： H01F27/24 ,  H01L23/492 ,  H01F27/30 ,  H01F3/14

CPC分类号： H01F27/24 ,  H01F3/14 ,  H01F17/04 ,  H01F27/306 ,  H01L23/492 ,  H01L23/49822 ,  H01L23/50 ,  H01L25/00 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/18161

摘要： A system in package module assembly is provided, and includes: a substrate (10), and a chip (12), an inductor (15), and an electrical element (17) that are electrically connected to the substrate. The substrate includes a first surface (111), a second surface (112) opposite to the first surface, and an accommodation groove (113). The accommodation groove passes through the second surface and the first surface. The inductor includes a magnetic core (151) and an inductive coil (153). The magnetic core includes a base (154) and a protrusion (155) disposed on an outer surface of the base. The outer surface on which the protrusion is disposed and that is of the base abuts on the second surface. The protrusion is accommodated in the accommodation groove. The inductive coil is disposed in the protrusion. A system in package module and an electronic device are further provided.