公开(公告)号：US20240363392A1

公开(公告)日：2024-10-31

申请号：US18765940

申请日：2024-07-08

Applicant: Applied Materials, Inc.

Inventor： Daihua Zhang ,  Yingdong Luo ,  Mingwei Zhu ,  Hou T. Ng ,  Sivapackia Ganapathiappan ,  Nag B. Patibandla

IPC: H01L21/70 ,  H01L21/02 ,  H01L21/027 ,  H01L25/075 ,  H01L27/15 ,  H01L33/00 ,  H01L33/44 ,  H01L33/50 ,  H01L33/58 ,  H01L33/62

CPC classification number: H01L21/70 ,  H01L21/02104 ,  H01L21/027 ,  H01L21/707 ,  H01L25/0753 ,  H01L27/153 ,  H01L33/00 ,  H01L33/0093 ,  H01L33/44 ,  H01L33/505 ,  H01L33/58 ,  H01L33/62 ,  H01L2933/0041 ,  H01L2933/0058 ,  H01L2933/0066

Abstract: A multi-color display includes a backplane having backplane circuitry, an array of micro-LEDs electrically integrated with backplane circuitry of the backplane, a color conversion layer over each of a plurality of light emitting diodes, and a plurality of isolation walls separating adjacent micro-LEDs of the array.

公开(公告)号：US12020978B2

公开(公告)日：2024-06-25

申请号：US17137500

申请日：2020-12-30

Applicant: Texas Instruments Incorporated

Inventor： Sam Gnana Sabapathy

IPC: G01R31/317 ,  G01R31/3187 ,  G06F30/30 ,  H01L21/70

CPC classification number: H01L21/70 ,  G01R31/31716 ,  G06F30/30 ,  G01R31/3187

Abstract: A packaged integrated circuit (IC) chip that provides input/output (I/O) signal fail safe verification is disclosed. The packaged IC chip includes a first processing unit, a first control peripheral coupled to receive a first processed signal from the processing unit and to provide an output signal, and compare logic. The compare logic is coupled to receive the output signal and a comparison signal, to compare the output signal and the comparison signal, and to provide an error signal responsive to a difference between the output signal and the comparison signal.

公开(公告)号：US20230253377A1

公开(公告)日：2023-08-10

申请号：US18304087

申请日：2023-04-20

Applicant: eLux Inc.

Inventor： Paul J Schuele ,  Kenji Sasaki ,  Kurt Ulmer ,  Jong-Jan Lee

IPC: H01L25/075 ,  H01L33/48 ,  H01L33/38 ,  H01L21/673 ,  H01L21/70

CPC classification number: H01L25/0753 ,  H01L33/486 ,  H01L33/38 ,  H01L21/67316 ,  H01L21/67343 ,  H01L21/70 ,  H01L2933/0033 ,  H01L2933/0066

Abstract: A microLED mass transfer stamping system includes a stamp substrate with an array of trap sites, each configured with a columnar-shaped recess to temporarily secure a keel extended from a bottom surface of a microLED. In the case of surface mount microLEDs, the keel is electrically nonconductive. In the case of vertical microLEDs, the keel is an electrically conductive second electrode. The stamping system also includes a fluidic assembly carrier substrate with an array of wells having a pitch separating adjacent wells that matches the pitch separating the stamp substrate trap sites. A display substrate includes an array of microLED pads with the same pitch as the trap sites. The stamp substrate top surface is pressed against the display substrate, with each trap site interfacing a corresponding microLED site, and the microLEDs are transferred. Fluidic assembly stamp substrates are also presented for use with microLEDs having keels or axial leads.

公开(公告)号：US20190189464A1

公开(公告)日：2019-06-20

申请号：US16327713

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Harold W. Kennel ,  Patrick Morrow ,  Rishabh Mehandru ,  Stephen M. Cea

IPC: H01L21/322 ,  H01L21/265 ,  H01L21/768 ,  H01L23/26

CPC classification number: H01L21/3226 ,  H01L21/26506 ,  H01L21/3221 ,  H01L21/38 ,  H01L21/70 ,  H01L21/768 ,  H01L23/26

Abstract: Methods and apparatus for gettering impurities in semiconductors are disclosed. A disclosed example multilayered die includes a substrate material, a component layer below the substrate material, and an impurity attractant region disposed in the substrate material.

公开(公告)号：US10083933B2

公开(公告)日：2018-09-25

申请号：US14976484

申请日：2015-12-21

Applicant: EV GROUP E. THALLNER GMBH

Inventor： Thomas Plach ,  Kurt Hingerl ,  Markus Wimplinger ,  Christoph Flotgen

IPC: H01L23/00 ,  H01L21/18 ,  H01L21/20 ,  H01L21/762 ,  H01L21/70

CPC classification number: H01L24/83 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/70 ,  H01L21/76251 ,  H01L24/80 ,  H01L2224/80907 ,  H01L2224/83009 ,  H01L2224/83894 ,  H01L2224/83907 ,  H01L2924/01001 ,  H01L2924/01007 ,  H01L2924/01008 ,  H01L2924/01018 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106

Abstract: A method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate according to the following steps: forming a reservoir in a surface layer on the first contact surface, at least partially filling the reservoir with a first educt or a first group of educts, contacting the first contact surface with the second contact surface for formation of a prebond connection, and forming a permanent bond between the first and second contact surface, at least partially strengthened by the reaction of the first educt with a second educt contained in a reaction layer of the second substrate.

公开(公告)号：US09640421B2

公开(公告)日：2017-05-02

申请号：US14950902

申请日：2015-11-24

Applicant: Artilux, Inc

Inventor： Szu-Lin Cheng ,  Shu-Lu Chen

IPC: H01L31/18 ,  H01L31/113 ,  H01L31/062 ,  H01L21/70 ,  H01L27/144 ,  H01L21/8234 ,  H01L31/0216 ,  H01L29/78 ,  H01L31/105 ,  H01L31/028 ,  H01L21/77 ,  H01L31/02 ,  H01L31/0232

CPC classification number: H01L31/02019 ,  H01L21/70 ,  H01L21/77 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53271 ,  H01L27/1443 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/14689 ,  H01L29/0657 ,  H01L29/78 ,  H01L31/02005 ,  H01L31/02161 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/105 ,  H01L31/18 ,  H01L31/1808 ,  H01L31/1868 ,  H01L31/1876

Abstract: Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.

公开(公告)号：US09583584B2

公开(公告)日：2017-02-28

申请号：US14795984

申请日：2015-07-10

Applicant: GLOBALFOUNDRIES, INC. ,  International Business Machines Corporation

Inventor： Chanro Park ,  Injo Ok

IPC: H01L21/70 ,  H01L29/49 ,  H01L29/66 ,  H01L21/82

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/70 ,  H01L21/82 ,  H01L21/82345 ,  H01L21/823456 ,  H01L29/66545

Abstract: Integrated circuits and methods for producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a work function layer overlying a substrate and a plurality of dielectric columns. The dielectric columns and the substrate define a short region having a short region width and a long region having a long region width greater than the short region width. The work function layer is recessed in the long region to a long region work function height that is between a dielectric column top surface and a substrate top surface. The work function layer is also recessed in the short region to a short region work function height that is between the dielectric column top surface and the substrate top surface. Recessing the work function layer in the long and short regions is conducted in the absence of lithography techniques.

Abstract translation: 提供了集成电路及其制造方法。 在示例性实施例中，用于制造集成电路的方法包括形成覆盖在基板和多个电介质柱上的功函数层。 电介质柱和衬底限定具有短区域宽度的短区域和具有大于短区域宽度的长区域宽度的长区域。 工作功能层在长区域中凹陷到介电柱顶表面和基板顶表面之间的长区域功函数高度。 工作功能层也在短区域中凹陷到介电柱顶表面和衬底顶表面之间的短区域功函数高度。 在没有光刻技术的情况下，在长和短区域内嵌入功函数层。

公开(公告)号：US20160174367A1

公开(公告)日：2016-06-16

申请号：US14893049

申请日：2014-05-21

Applicant: TRANSIENT ELECTRONICS, INC.

Inventor： Christopher Poirier ,  Anthony Campbell ,  John A. Rogers ,  Winston E. Henderson

IPC: H05K1/02 ,  H05K13/00

CPC classification number: H05K1/0275 ,  B02C23/00 ,  H01L21/70 ,  H01L23/04 ,  H01L23/57 ,  H01L2924/0002 ,  H05B3/06 ,  H05K1/02 ,  H05K13/00 ,  H05K2203/178 ,  Y10T29/49002 ,  H01L2924/00

Abstract: Systems and methods of the invention generally relate to altering the functionality of a non-transient electronic device. A container holding an agent is located proximal to a non-tansient electronic device capable of performing at least one function. The agent is capable of rendering the device incapable of performing the at least one function. The container is configured to controllably release the agent to the electronic device in a variety of passive and active eventualities.

Abstract translation: 本发明的系统和方法通常涉及改变非瞬态电子设备的功能。 容纳药剂的容器位于能够执行至少一种功能的非调味电子设备的近侧。 代理能够使设备不能执行至少一个功能。 容器被配置为以各种被动和主动的可能性可控地将代理释放到电子设备。

公开(公告)号：US20160148959A1

公开(公告)日：2016-05-26

申请号：US14950902

申请日：2015-11-24

Applicant: Artilux, Inc

Inventor： Szu-Lin Cheng ,  Shu-Lu Chen

IPC: H01L27/144 ,  H01L21/8234 ,  H01L23/535 ,  H01L31/028 ,  H01L31/0216 ,  H01L29/78 ,  H01L31/105 ,  H01L31/18 ,  H01L21/02

CPC classification number: H01L31/02019 ,  H01L21/70 ,  H01L21/77 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53271 ,  H01L27/1443 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/14689 ,  H01L29/0657 ,  H01L29/78 ,  H01L31/02005 ,  H01L31/02161 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/105 ,  H01L31/18 ,  H01L31/1808 ,  H01L31/1868 ,  H01L31/1876

Abstract: Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.

Abstract translation: 这里介绍的各种技术的示例包括但不限于在浅沟槽隔离形成期间的台面高度调节方法，通过第一种方法的晶体管和多吸收层方法。 如下面进一步描述的，本文介绍的技术包括可以单独地和/或共同地解决或减轻在相同衬底上制造PD和晶体管所涉及的一个或多个传统限制的各种方面，例如上述可靠性，性能和过程 温度问题。

公开(公告)号：US20150054065A1

公开(公告)日：2015-02-26

申请号：US14532571

申请日：2014-11-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Cheng-Cheng Kuo ,  Ming Zhu

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/088 ,  H01L21/70 ,  H01L21/823487 ,  H01L29/0657 ,  H01L29/41783 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/7827

Abstract: A method of making a tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A source region is formed as a top portion of the frustoconical protrusion structure. A series connection and a parallel connection are made among TFET devices units.

Abstract translation: 公开了一种制造隧道场效应晶体管（TFET）器件的方法。 截头圆锥形突起结构设置在衬底上并突出到衬底平面之外。 在基板上形成隔离特征。 漏极区域设置在与截头圆锥形突起结构相邻的衬底上，并延伸到截头圆锥形突起结构的底部作为升高的漏极区域。 源区域形成为截头圆锥形突起结构的顶部。 在TFET器件单元之间进行串联和并联连接。